From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Samarth Saxena <samarths@cadence.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Subject: Re: [CXL HDM DECODER PROGRAMMING] - Question: Does Qemu program HDM decoder register of the CXL endpoint?
Date: Mon, 24 Jan 2022 10:52:45 +0000 [thread overview]
Message-ID: <20220124105245.00006aa1@Huawei.com> (raw)
In-Reply-To: <DM8PR07MB8920E2DE0A0435025B4C0E2FDD5D9@DM8PR07MB8920.namprd07.prod.outlook.com>
On Sun, 23 Jan 2022 16:13:29 +0000
Samarth Saxena <samarths@cadence.com> wrote:
> Hi All,
>
> I had a question about the CXL HDM Decoder register programming.
> Is there any part of Qemu, that automatically programs the enable bit
> of the HDM decoder register in the Component registers of the CXL
> endpoint? The CDR (component registers) are hosted inside the memory
> of the CXL endpoint.
Hi Samarth,
Given upstream QEMU doesn't support any CXL emulation at all currently
the answer to that is a no :)
I hope to post a v4 patch series for CXL support later this week.
Once that's out perhaps we can pick up this question again.
Thanks,
Jonathan
>
> Regards,
> [CadenceLogoRed185Regcopy1583174817new51584636989.png]<https://www.cadence.com/en_US/home.html>
> Samarth Saxena
> Sr Principal Software Engineer
> T: 911204308300
> [UIcorrectsize1583179003.png]<https://www.cadence.com/en_US/home.html>
> [16066EmailSignatureFortune100Best2021White92x1271617625037.png]<https://www.cadence.com/en_US/home/company/careers.html>
>
>
>
>
>
prev parent reply other threads:[~2022-01-24 10:54 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-23 16:13 [CXL HDM DECODER PROGRAMMING] - Question: Does Qemu program HDM decoder register of the CXL endpoint? Samarth Saxena
2022-01-24 10:52 ` Jonathan Cameron via [this message]
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