diff for duplicates of <202201250552.SryPX3ni-lkp@intel.com> diff --git a/a/1.txt b/N1/1.txt index e7ef732..112f95b 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,7 +1,7 @@ tree: https://github.com/esmil/linux visionfive head: fdbe623707a8f3f9b9d2cb3c4c240299a12b8302 commit: c17f07c367229d46348e9005d004d8b3416637bc [59/63] RISC-V: Enable SIFIVE_L2_FLUSH for StarFive SoCs -config: riscv-randconfig-r015-20220124 (https://download.01.org/0day-ci/archive/20220125/202201250552.SryPX3ni-lkp@intel.com/config) +config: riscv-randconfig-r015-20220124 (https://download.01.org/0day-ci/archive/20220125/202201250552.SryPX3ni-lkp(a)intel.com/config) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 7b3d30728816403d1fd73cc5082e9fb761262bce) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross @@ -72,7 +72,7 @@ c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-0 c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 163 #endif c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 164 -:::::: The code at line 158 was first introduced by commit +:::::: The code@line 158 was first introduced by commit :::::: c6649e71d37210bc4c33eada849aeda98c823de9 sifive/sifive_l2_cache: Add sifive_l2_flush64_range function :::::: TO: Tom <support@vamrs.com> @@ -80,4 +80,4 @@ c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-0 --- 0-DAY CI Kernel Test Service, Intel Corporation -https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org +https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org diff --git a/a/content_digest b/N1/content_digest index 2367012..0cffbaa 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,16 +1,13 @@ "From\0kernel test robot <lkp@intel.com>\0" "Subject\0[esmil:visionfive 59/63] drivers/soc/sifive/sifive_l2_cache.c:158:3: error: implicit declaration of function 'writeq'\0" "Date\0Tue, 25 Jan 2022 06:23:27 +0800\0" - "To\0Emil Renner Berthing <kernel@esmil.dk>\0" - "Cc\0llvm@lists.linux.dev" - kbuild-all@lists.01.org - " linux-kernel@vger.kernel.org\0" - "\00:1\0" + "To\0kbuild-all@lists.01.org\0" + "\01:1\0" "b\0" "tree: https://github.com/esmil/linux visionfive\n" "head: fdbe623707a8f3f9b9d2cb3c4c240299a12b8302\n" "commit: c17f07c367229d46348e9005d004d8b3416637bc [59/63] RISC-V: Enable SIFIVE_L2_FLUSH for StarFive SoCs\n" - "config: riscv-randconfig-r015-20220124 (https://download.01.org/0day-ci/archive/20220125/202201250552.SryPX3ni-lkp@intel.com/config)\n" + "config: riscv-randconfig-r015-20220124 (https://download.01.org/0day-ci/archive/20220125/202201250552.SryPX3ni-lkp(a)intel.com/config)\n" "compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 7b3d30728816403d1fd73cc5082e9fb761262bce)\n" "reproduce (this is a W=1 build):\n" " wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross\n" @@ -81,7 +78,7 @@ "c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 163 #endif\n" "c6649e71d37210 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 164 \n" "\n" - ":::::: The code at line 158 was first introduced by commit\n" + ":::::: The code@line 158 was first introduced by commit\n" ":::::: c6649e71d37210bc4c33eada849aeda98c823de9 sifive/sifive_l2_cache: Add sifive_l2_flush64_range function\n" "\n" ":::::: TO: Tom <support@vamrs.com>\n" @@ -89,6 +86,6 @@ "\n" "---\n" "0-DAY CI Kernel Test Service, Intel Corporation\n" - https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org + https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org -94a92d41463449c17642163a08d7f8fa500337172d1f4d78ebad288cfad6b29a +e1d7183582f72ebefac5c6ee3466d9571e839530015e23649540fba39765cf4b
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