From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: multipart/mixed; boundary="===============2273492656370804968==" MIME-Version: 1.0 From: kernel test robot To: kbuild-all@lists.01.org Subject: [intel-lts:5.4/preempt-rt 14488/20929] drivers/spi/spi-dw-pci.c:155:5: sparse: sparse: undefined preprocessor identifier 'CONFIG_PM' Date: Wed, 26 Jan 2022 06:51:40 +0800 Message-ID: <202201260630.jy313RXW-lkp@intel.com> List-Id: --===============2273492656370804968== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable tree: https://github.com/intel/linux-intel-lts.git 5.4/preempt-rt head: 196e38246d15096460031f4a17913922c006b12d commit: 2e228f3df9479e9e061cc7e0b7aba0c071ea22bf [14488/20929] REVERT-ME: T= emporary Enable D0i3 flow for PSE IOs config: x86_64-randconfig-s022-20220124 (https://download.01.org/0day-ci/ar= chive/20220126/202201260630.jy313RXW-lkp(a)intel.com/config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 reproduce: # apt-get install sparse # sparse version: v0.6.4-dirty # https://github.com/intel/linux-intel-lts/commit/2e228f3df9479e9e0= 61cc7e0b7aba0c071ea22bf git remote add intel-lts https://github.com/intel/linux-intel-lts.g= it git fetch --no-tags intel-lts 5.4/preempt-rt git checkout 2e228f3df9479e9e061cc7e0b7aba0c071ea22bf # save the config file to linux build tree mkdir build_dir make W=3D1 C=3D1 CF=3D'-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=3D= build_dir ARCH=3Dx86_64 SHELL=3D/bin/bash drivers/spi/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot sparse warnings: (new ones prefixed by >>) >> drivers/spi/spi-dw-pci.c:155:5: sparse: sparse: undefined preprocessor i= dentifier 'CONFIG_PM' vim +/CONFIG_PM +155 drivers/spi/spi-dw-pci.c 154 = > 155 #if CONFIG_PM 156 static int dw_spi_runtime_suspend(struct device *dev) 157 { 158 struct dw_spi *dws =3D dev_get_drvdata(dev); 159 unsigned long j0, j1, delay; 160 u32 d0i3c_reg; 161 u32 cgsr_reg; 162 = 163 delay =3D msecs_to_jiffies(100); 164 j0 =3D jiffies; 165 j1 =3D j0 + delay; 166 = 167 = 168 cgsr_reg =3D dw_readl(dws, PSE_SPI_CGSR); 169 dw_writel(dws, PSE_SPI_CGSR, PSE_SPI_D0I3_RR); 170 = 171 d0i3c_reg =3D dw_readl(dws, PSE_SPI_D0I3C); 172 = 173 if (d0i3c_reg & PSE_SPI_D0I3_CIP) { 174 dev_info(dev, "%s d0i3c CIP detected", __func__); 175 } else { 176 dw_writel(dws, PSE_SPI_D0I3C, PSE_SPI_D0I3_EN); 177 d0i3c_reg =3D dw_readl(dws, PSE_SPI_D0I3C); 178 } 179 = 180 while (time_before(jiffies, j1)) { 181 d0i3c_reg =3D dw_readl(dws, PSE_SPI_D0I3C); 182 if (!(d0i3c_reg & PSE_SPI_D0I3_CIP)) 183 break; 184 } 185 = 186 if (d0i3c_reg & PSE_SPI_D0I3_CIP) 187 dev_info(dev, "%s: timeout waiting CIP to be cleared", 188 __func__); 189 = 190 return 0; 191 } 192 = --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org --===============2273492656370804968==--