From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 44BE32CA2 for ; Thu, 27 Jan 2022 00:53:20 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DD02A1FB; Wed, 26 Jan 2022 16:53:19 -0800 (PST) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 49A003F7D8; Wed, 26 Jan 2022 16:53:18 -0800 (PST) Date: Thu, 27 Jan 2022 00:53:04 +0000 From: Andre Przywara To: Jesse Taube Cc: devicetree@vger.kernel.org, robh+dt@kernel.org, Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Chris Morgan Subject: Re: [PATCH] ARM: dts: suniv: Add MMC and clock macros. Message-ID: <20220127005304.06215ae8@slackpad.fritz.box> In-Reply-To: References: <20220125011352.2691365-1-Mr.Bossman075@gmail.com> <20220126235726.03abdab4@slackpad.fritz.box> Organization: Arm Ltd. X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 26 Jan 2022 19:12:05 -0500 Jesse Taube wrote: > On 1/26/22 18:57, Andre Przywara wrote: > > On Mon, 24 Jan 2022 20:13:52 -0500 > > Jesse Taube wrote: > > > > Hi Jesse, > > > > I understand that get_maintainers.pl suggested this CC: list, but you > > should add sunxi people and linux-arm kernel ML. Doing that now. > Uh yeah that makes sense in hind sight. > >> Include clock and reset macros and replace magic numbers. > >> Add MMC node. > > > > This patch itself does not do much, does it? You would at least need to > > enable that in the board dts. > True it doesn't do much just so that its in both u-boot and linux. > > And this should be multiple patches: > > 1) replace numbers with macros (part of this patch) > > 2) Add the MMC compatible string combo to the the bindings doc > > 3) Add the *two* MMC nodes and at least the pinctrl node for MMC0 to the > > SoC .dtsi (partly in this patch) > > 4) Enable the MMC and the card detect pin in the Nano board .dts > > > > I checked that the macros names match the numbers they replace, so > > you can add my R-b: on that patch 1 (if you follow my suggestion). > > The MMC node also seems to look sane. > That seems okay. > >> > >> Signed-off-by: Mesih Kilinc > > > > It is not evident why Mesih's S-o-b: is in here? The patch seems to be > > authored and sent by you? Either you make him the author if that is his > > patch originally, or you put him just as Cc: or in Suggested-by:, maybe. > I did write the patch after I wrote it I was looking at his github and > he had almost the same patch. Yeah, not really surprising, there are only so many ways to write a DT. I guess he never sent it, and since you wrote it, it's yours, so just add him in Cc:, since he was involved in the F1C100s upstreaming. Cheers, Andre > > Cheers, > > Andre > > > >> Signed-off-by: Jesse Taube > >> --- > >> arch/arm/boot/dts/suniv-f1c100s.dtsi | 41 +++++++++++++++++++++++----- > >> 1 file changed, 34 insertions(+), 7 deletions(-) > >> > >> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi > >> index 6100d3b75f61..32872bb29917 100644 > >> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi > >> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi > >> @@ -4,6 +4,9 @@ > >> * Copyright 2018 Mesih Kilinc > >> */ > >> > >> +#include > >> +#include > >> + > >> / { > >> #address-cells = <1>; > >> #size-cells = <1>; > >> @@ -82,7 +85,7 @@ pio: pinctrl@1c20800 { > >> compatible = "allwinner,suniv-f1c100s-pinctrl"; > >> reg = <0x01c20800 0x400>; > >> interrupts = <38>, <39>, <40>; > >> - clocks = <&ccu 37>, <&osc24M>, <&osc32k>; > >> + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; > >> clock-names = "apb", "hosc", "losc"; > >> gpio-controller; > >> interrupt-controller; > >> @@ -93,6 +96,11 @@ uart0_pe_pins: uart0-pe-pins { > >> pins = "PE0", "PE1"; > >> function = "uart0"; > >> }; > >> + > >> + mmc0_pins: mmc0-pins { > >> + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; > >> + function = "mmc0"; > >> + }; > >> }; > >> > >> timer@1c20c00 { > >> @@ -108,14 +116,33 @@ wdt: watchdog@1c20ca0 { > >> reg = <0x01c20ca0 0x20>; > >> }; > >> > >> + mmc0: mmc@1c0f000 { > >> + compatible = "allwinner,suniv-f1c100s-mmc", > >> + "allwinner,sun7i-a20-mmc"; > >> + reg = <0x01c0f000 0x1000>; > >> + clocks = <&ccu CLK_BUS_MMC0>, > >> + <&ccu CLK_MMC0>, > >> + <&ccu CLK_MMC0_OUTPUT>, > >> + <&ccu CLK_MMC0_SAMPLE>; > >> + clock-names = "ahb", "mmc", "output", "sample"; > >> + resets = <&ccu RST_BUS_MMC0>; > >> + reset-names = "ahb"; > >> + interrupts = <23>; > >> + pinctrl-names = "default"; > >> + pinctrl-0 = <&mmc0_pins>; > >> + status = "disabled"; > >> + #address-cells = <1>; > >> + #size-cells = <0>; > >> + }; > >> + > >> uart0: serial@1c25000 { > >> compatible = "snps,dw-apb-uart"; > >> reg = <0x01c25000 0x400>; > >> interrupts = <1>; > >> reg-shift = <2>; > >> reg-io-width = <4>; > >> - clocks = <&ccu 38>; > >> - resets = <&ccu 24>; > >> + clocks = <&ccu CLK_BUS_UART0>; > >> + resets = <&ccu RST_BUS_UART0>; > >> status = "disabled"; > >> }; > >> > >> @@ -125,8 +152,8 @@ uart1: serial@1c25400 { > >> interrupts = <2>; > >> reg-shift = <2>; > >> reg-io-width = <4>; > >> - clocks = <&ccu 39>; > >> - resets = <&ccu 25>; > >> + clocks = <&ccu CLK_BUS_UART1>; > >> + resets = <&ccu RST_BUS_UART1>; > >> status = "disabled"; > >> }; > >> > >> @@ -136,8 +163,8 @@ uart2: serial@1c25800 { > >> interrupts = <3>; > >> reg-shift = <2>; > >> reg-io-width = <4>; > >> - clocks = <&ccu 40>; > >> - resets = <&ccu 26>; > >> + clocks = <&ccu CLK_BUS_UART2>; > >> + resets = <&ccu RST_BUS_UART2>; > >> status = "disabled"; > >> }; > >> }; > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BAF6C433F5 for ; Thu, 27 Jan 2022 00:55:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hBDVJXbwNDI71fKvLwIseZYUpMSz3u/rV3W6WB6yGvU=; b=jjmrkhxaJH+5YM u8NwJ8bsxFtNjUEJdZ47t45M8YpF8ge3vV+AHcrnHNIkCB1ZNQOgrkWrosDgJHWtzjbnjC9Fh4F3F MOAcKyjO16Bt0hqsaSj7Dtgb85xFiYkIcCtJtoVnEaxT3Phq95ajLoyFym5896+hfXacz1h/mJR0D y7EbchUchqBGhmrFUAnDa1WrMgHJme2pJRLZDUU8UySP8rGI8IueGad1ouKsNIAqBAVkARopTUGLg oMrrLqYRRaJv6Yf/rdspQEChXZuj2RofEmnRa2PRkf3VjVw6D3f5ufLHdKboLe5yo51DN6aAVvz83 A0M475QOXSyBVjUo75aQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCt2S-00DtLN-QH; Thu, 27 Jan 2022 00:53:24 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCt2O-00DtKX-Lf for linux-arm-kernel@lists.infradead.org; Thu, 27 Jan 2022 00:53:22 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DD02A1FB; Wed, 26 Jan 2022 16:53:19 -0800 (PST) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 49A003F7D8; Wed, 26 Jan 2022 16:53:18 -0800 (PST) Date: Thu, 27 Jan 2022 00:53:04 +0000 From: Andre Przywara To: Jesse Taube Cc: devicetree@vger.kernel.org, robh+dt@kernel.org, Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Chris Morgan Subject: Re: [PATCH] ARM: dts: suniv: Add MMC and clock macros. Message-ID: <20220127005304.06215ae8@slackpad.fritz.box> In-Reply-To: References: <20220125011352.2691365-1-Mr.Bossman075@gmail.com> <20220126235726.03abdab4@slackpad.fritz.box> Organization: Arm Ltd. X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220126_165320_846173_3D46C913 X-CRM114-Status: GOOD ( 32.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 26 Jan 2022 19:12:05 -0500 Jesse Taube wrote: > On 1/26/22 18:57, Andre Przywara wrote: > > On Mon, 24 Jan 2022 20:13:52 -0500 > > Jesse Taube wrote: > > > > Hi Jesse, > > > > I understand that get_maintainers.pl suggested this CC: list, but you > > should add sunxi people and linux-arm kernel ML. Doing that now. > Uh yeah that makes sense in hind sight. > >> Include clock and reset macros and replace magic numbers. > >> Add MMC node. > > > > This patch itself does not do much, does it? You would at least need to > > enable that in the board dts. > True it doesn't do much just so that its in both u-boot and linux. > > And this should be multiple patches: > > 1) replace numbers with macros (part of this patch) > > 2) Add the MMC compatible string combo to the the bindings doc > > 3) Add the *two* MMC nodes and at least the pinctrl node for MMC0 to the > > SoC .dtsi (partly in this patch) > > 4) Enable the MMC and the card detect pin in the Nano board .dts > > > > I checked that the macros names match the numbers they replace, so > > you can add my R-b: on that patch 1 (if you follow my suggestion). > > The MMC node also seems to look sane. > That seems okay. > >> > >> Signed-off-by: Mesih Kilinc > > > > It is not evident why Mesih's S-o-b: is in here? The patch seems to be > > authored and sent by you? Either you make him the author if that is his > > patch originally, or you put him just as Cc: or in Suggested-by:, maybe. > I did write the patch after I wrote it I was looking at his github and > he had almost the same patch. Yeah, not really surprising, there are only so many ways to write a DT. I guess he never sent it, and since you wrote it, it's yours, so just add him in Cc:, since he was involved in the F1C100s upstreaming. Cheers, Andre > > Cheers, > > Andre > > > >> Signed-off-by: Jesse Taube > >> --- > >> arch/arm/boot/dts/suniv-f1c100s.dtsi | 41 +++++++++++++++++++++++----- > >> 1 file changed, 34 insertions(+), 7 deletions(-) > >> > >> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi > >> index 6100d3b75f61..32872bb29917 100644 > >> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi > >> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi > >> @@ -4,6 +4,9 @@ > >> * Copyright 2018 Mesih Kilinc > >> */ > >> > >> +#include > >> +#include > >> + > >> / { > >> #address-cells = <1>; > >> #size-cells = <1>; > >> @@ -82,7 +85,7 @@ pio: pinctrl@1c20800 { > >> compatible = "allwinner,suniv-f1c100s-pinctrl"; > >> reg = <0x01c20800 0x400>; > >> interrupts = <38>, <39>, <40>; > >> - clocks = <&ccu 37>, <&osc24M>, <&osc32k>; > >> + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; > >> clock-names = "apb", "hosc", "losc"; > >> gpio-controller; > >> interrupt-controller; > >> @@ -93,6 +96,11 @@ uart0_pe_pins: uart0-pe-pins { > >> pins = "PE0", "PE1"; > >> function = "uart0"; > >> }; > >> + > >> + mmc0_pins: mmc0-pins { > >> + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; > >> + function = "mmc0"; > >> + }; > >> }; > >> > >> timer@1c20c00 { > >> @@ -108,14 +116,33 @@ wdt: watchdog@1c20ca0 { > >> reg = <0x01c20ca0 0x20>; > >> }; > >> > >> + mmc0: mmc@1c0f000 { > >> + compatible = "allwinner,suniv-f1c100s-mmc", > >> + "allwinner,sun7i-a20-mmc"; > >> + reg = <0x01c0f000 0x1000>; > >> + clocks = <&ccu CLK_BUS_MMC0>, > >> + <&ccu CLK_MMC0>, > >> + <&ccu CLK_MMC0_OUTPUT>, > >> + <&ccu CLK_MMC0_SAMPLE>; > >> + clock-names = "ahb", "mmc", "output", "sample"; > >> + resets = <&ccu RST_BUS_MMC0>; > >> + reset-names = "ahb"; > >> + interrupts = <23>; > >> + pinctrl-names = "default"; > >> + pinctrl-0 = <&mmc0_pins>; > >> + status = "disabled"; > >> + #address-cells = <1>; > >> + #size-cells = <0>; > >> + }; > >> + > >> uart0: serial@1c25000 { > >> compatible = "snps,dw-apb-uart"; > >> reg = <0x01c25000 0x400>; > >> interrupts = <1>; > >> reg-shift = <2>; > >> reg-io-width = <4>; > >> - clocks = <&ccu 38>; > >> - resets = <&ccu 24>; > >> + clocks = <&ccu CLK_BUS_UART0>; > >> + resets = <&ccu RST_BUS_UART0>; > >> status = "disabled"; > >> }; > >> > >> @@ -125,8 +152,8 @@ uart1: serial@1c25400 { > >> interrupts = <2>; > >> reg-shift = <2>; > >> reg-io-width = <4>; > >> - clocks = <&ccu 39>; > >> - resets = <&ccu 25>; > >> + clocks = <&ccu CLK_BUS_UART1>; > >> + resets = <&ccu RST_BUS_UART1>; > >> status = "disabled"; > >> }; > >> > >> @@ -136,8 +163,8 @@ uart2: serial@1c25800 { > >> interrupts = <3>; > >> reg-shift = <2>; > >> reg-io-width = <4>; > >> - clocks = <&ccu 40>; > >> - resets = <&ccu 26>; > >> + clocks = <&ccu CLK_BUS_UART2>; > >> + resets = <&ccu RST_BUS_UART2>; > >> status = "disabled"; > >> }; > >> }; > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel