From: Kajol Jain <kjain@linux.ibm.com>
To: mpe@ellerman.id.au
Cc: kjain@linux.ibm.com, atrajeev@linux.vnet.ibm.com,
maddy@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org,
rnsastry@linux.ibm.com
Subject: [PATCH 04/20] selftest/powerpc/pmu: Add utility functions to post process the mmap buffer
Date: Thu, 27 Jan 2022 12:49:56 +0530 [thread overview]
Message-ID: <20220127072012.662451-5-kjain@linux.ibm.com> (raw)
In-Reply-To: <20220127072012.662451-1-kjain@linux.ibm.com>
Add couple of basic utility functions to post process the
mmap buffer. It includes function to read the total
number of samples present in the mmap buffer and function
to get the address of the first sample.
Add function "get_intr_regs" which will return pointer to
interrupt registers present in the sample, incase sample
type PERF_SAMPLE_REGS_INTR is set.
Add functions "get_reg_value" which can be used to read any
interrupt register value from a given sample.
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
---
.../powerpc/pmu/sampling_tests/misc.c | 175 ++++++++++++++++++
.../powerpc/pmu/sampling_tests/misc.h | 4 +
2 files changed, 179 insertions(+)
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
index fcd139c95971..5712df1bd3c2 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.c
@@ -2,6 +2,7 @@
/*
* Copyright 2022, Athira Rajeev, IBM Corp.
* Copyright 2022, Madhavan Srinivasan, IBM Corp.
+ * Copyright 2022, Kajol Jain, IBM Corp.
*/
#include <unistd.h>
@@ -330,3 +331,177 @@ void *__event_read_samples(void *sample_buff, size_t *size, u64 *sample_count)
}
return NULL;
}
+
+int collect_samples(void *sample_buff)
+{
+ u64 sample_count;
+ size_t size = 0;
+
+ __event_read_samples(sample_buff, &size, &sample_count);
+ return sample_count;
+}
+
+static void *perf_read_first_sample(void *sample_buff, size_t *size)
+{
+ return __event_read_samples(sample_buff, size, NULL);
+}
+
+u64 *get_intr_regs(struct event *event, void *sample_buff)
+{
+ u64 type = event->attr.sample_type;
+ u64 *intr_regs;
+ size_t size = 0;
+
+ if ((type ^ PERF_SAMPLE_REGS_INTR))
+ return NULL;
+
+ intr_regs = (u64 *)perf_read_first_sample(sample_buff, &size);
+ if (!intr_regs)
+ return NULL;
+
+ /*
+ * First entry in the sample buffer used to specify
+ * PERF_SAMPLE_REGS_ABI_64, skip perf regs abi to access
+ * interrupt registers.
+ */
+ ++intr_regs;
+
+ return intr_regs;
+}
+
+static const unsigned int __perf_reg_mask(const char *register_name)
+{
+ if (!strcmp(register_name, "R0"))
+ return 0;
+ else if (!strcmp(register_name, "R1"))
+ return 1;
+ else if (!strcmp(register_name, "R2"))
+ return 2;
+ else if (!strcmp(register_name, "R3"))
+ return 3;
+ else if (!strcmp(register_name, "R4"))
+ return 4;
+ else if (!strcmp(register_name, "R5"))
+ return 5;
+ else if (!strcmp(register_name, "R6"))
+ return 6;
+ else if (!strcmp(register_name, "R7"))
+ return 7;
+ else if (!strcmp(register_name, "R8"))
+ return 8;
+ else if (!strcmp(register_name, "R9"))
+ return 9;
+ else if (!strcmp(register_name, "R10"))
+ return 10;
+ else if (!strcmp(register_name, "R11"))
+ return 11;
+ else if (!strcmp(register_name, "R12"))
+ return 12;
+ else if (!strcmp(register_name, "R13"))
+ return 13;
+ else if (!strcmp(register_name, "R14"))
+ return 14;
+ else if (!strcmp(register_name, "R15"))
+ return 15;
+ else if (!strcmp(register_name, "R16"))
+ return 16;
+ else if (!strcmp(register_name, "R17"))
+ return 17;
+ else if (!strcmp(register_name, "R18"))
+ return 18;
+ else if (!strcmp(register_name, "R19"))
+ return 19;
+ else if (!strcmp(register_name, "R20"))
+ return 20;
+ else if (!strcmp(register_name, "R21"))
+ return 21;
+ else if (!strcmp(register_name, "R22"))
+ return 22;
+ else if (!strcmp(register_name, "R23"))
+ return 23;
+ else if (!strcmp(register_name, "R24"))
+ return 24;
+ else if (!strcmp(register_name, "R25"))
+ return 25;
+ else if (!strcmp(register_name, "R26"))
+ return 26;
+ else if (!strcmp(register_name, "R27"))
+ return 27;
+ else if (!strcmp(register_name, "R28"))
+ return 28;
+ else if (!strcmp(register_name, "R29"))
+ return 29;
+ else if (!strcmp(register_name, "R30"))
+ return 30;
+ else if (!strcmp(register_name, "R31"))
+ return 31;
+ else if (!strcmp(register_name, "NIP"))
+ return 32;
+ else if (!strcmp(register_name, "MSR"))
+ return 33;
+ else if (!strcmp(register_name, "ORIG_R3"))
+ return 34;
+ else if (!strcmp(register_name, "CTR"))
+ return 35;
+ else if (!strcmp(register_name, "LINK"))
+ return 36;
+ else if (!strcmp(register_name, "XER"))
+ return 37;
+ else if (!strcmp(register_name, "CCR"))
+ return 38;
+ else if (!strcmp(register_name, "SOFTE"))
+ return 39;
+ else if (!strcmp(register_name, "TRAP"))
+ return 40;
+ else if (!strcmp(register_name, "DAR"))
+ return 41;
+ else if (!strcmp(register_name, "DSISR"))
+ return 42;
+ else if (!strcmp(register_name, "SIER"))
+ return 43;
+ else if (!strcmp(register_name, "MMCRA"))
+ return 44;
+ else if (!strcmp(register_name, "MMCR0"))
+ return 45;
+ else if (!strcmp(register_name, "MMCR1"))
+ return 46;
+ else if (!strcmp(register_name, "MMCR2"))
+ return 47;
+ else if (!strcmp(register_name, "MMCR3"))
+ return 48;
+ else if (!strcmp(register_name, "SIER2"))
+ return 49;
+ else if (!strcmp(register_name, "SIER3"))
+ return 50;
+ else if (!strcmp(register_name, "PMC1"))
+ return 51;
+ else if (!strcmp(register_name, "PMC2"))
+ return 52;
+ else if (!strcmp(register_name, "PMC3"))
+ return 53;
+ else if (!strcmp(register_name, "PMC4"))
+ return 54;
+ else if (!strcmp(register_name, "PMC5"))
+ return 55;
+ else if (!strcmp(register_name, "PMC6"))
+ return 56;
+ else if (!strcmp(register_name, "SDAR"))
+ return 57;
+ else if (!strcmp(register_name, "SIAR"))
+ return 58;
+ else
+ return -1;
+}
+
+u64 get_reg_value(u64 *intr_regs, char *register_name)
+{
+ int register_bit_position;
+
+ register_bit_position = __perf_reg_mask(register_name);
+
+ if (register_bit_position < 0 || (!((platform_extended_mask >>
+ (register_bit_position - 1)) & 1)))
+ return -1;
+
+ return *(intr_regs + register_bit_position);
+}
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
index 8526c15d4c90..3cfe98716b1e 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
@@ -2,6 +2,7 @@
/*
* Copyright 2022, Athira Rajeev, IBM Corp.
* Copyright 2022, Madhavan Srinivasan, IBM Corp.
+ * Copyright 2022, Kajol Jain, IBM Corp.
*/
#include "../event.h"
@@ -57,3 +58,6 @@ static inline int is_pSeries(void)
void *event_sample_buf_mmap(int fd, int mmap_pages);
void *__event_read_samples(void *sample_buff, size_t *size, u64 *sample_count);
+int collect_samples(void *sample_buff);
+u64 *get_intr_regs(struct event *event, void *sample_buff);
+u64 get_reg_value(u64 *intr_regs, char *register_name);
--
2.27.0
next prev parent reply other threads:[~2022-01-27 7:24 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-27 7:19 [PATCH 00/20] Add perf sampling tests as part of selftest Kajol Jain
2022-01-27 7:19 ` [PATCH 01/20] selftest/powerpc/pmu: Include mmap_buffer field as part of struct event Kajol Jain
2022-01-27 7:19 ` [PATCH 02/20] selftest/powerpc/pmu: Add support for perf sampling tests Kajol Jain
2022-01-27 7:19 ` [PATCH 03/20] selftest/powerpc/pmu: Add macros to parse event codes Kajol Jain
2022-01-27 7:19 ` Kajol Jain [this message]
2022-01-27 7:19 ` [PATCH 05/20] selftest/powerpc/pmu: Add event_init_sampling function Kajol Jain
2022-01-27 7:19 ` [PATCH 06/20] selftest/powerpc/pmu: Add macros to extract mmcr fields Kajol Jain
2022-01-27 7:19 ` [PATCH 07/20] selftest/powerpc/pmu: Add macro to extract mmcr0/mmcr1 fields Kajol Jain
2022-01-27 7:20 ` [PATCH 08/20] selftest/powerpc/pmu: Add macro to extract mmcr3 and mmcra fields Kajol Jain
2022-01-27 7:20 ` [PATCH 09/20] selftest/powerpc/pmu/: Add interface test for mmcr0 exception bits Kajol Jain
2022-01-27 7:20 ` [PATCH 10/20] selftest/powerpc/pmu/: Add interface test for mmcr0_cc56run field Kajol Jain
2022-01-27 7:20 ` [PATCH 11/20] selftest/powerpc/pmu/: Add interface test for mmcr0_pmccext bit Kajol Jain
2022-01-27 7:20 ` [PATCH 12/20] selftest/powerpc/pmu/: Add interface test for mmcr0_pmcjce field Kajol Jain
2022-01-27 7:20 ` [PATCH 13/20] selftest/powerpc/pmu/: Add interface test for mmcr0_fc56 field using pmc1 Kajol Jain
2022-01-27 7:20 ` [PATCH 14/20] selftest/powerpc/pmu/: Add interface test for mmcr0_pmc56 using pmc5 Kajol Jain
2022-01-27 7:20 ` [PATCH 15/20] selftest/powerpc/pmu/: Add interface test for mmcr1_comb field Kajol Jain
2022-01-27 7:20 ` [PATCH 16/20] selftest/powerpc/pmu/: Add selftest for mmcr1 pmcxsel/unit/cache fields Kajol Jain
2022-03-10 7:49 ` Christophe Leroy
2022-03-10 12:11 ` Michael Ellerman
2022-03-10 12:29 ` kajoljain
2022-01-27 7:20 ` [PATCH 17/20] selftest/powerpc/pmu/: Add interface test for mmcr2_l2l3 field Kajol Jain
2022-01-27 7:20 ` [PATCH 18/20] selftest/powerpc/pmu/: Add interface test for mmcr2_fcs_fch fields Kajol Jain
2022-01-27 7:20 ` [PATCH 19/20] selftest/powerpc/pmu/: Add interface test for mmcr3_src fields Kajol Jain
2022-01-27 7:20 ` [PATCH 20/20] selftest/powerpc/pmu: Add interface test for mmcra register fields Kajol Jain
2022-03-02 12:41 ` [PATCH 00/20] Add perf sampling tests as part of selftest Michael Ellerman
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