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From: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 02/15] drm/i915: Extract skl_ddb_entry_init()
Date: Thu, 27 Jan 2022 10:16:47 +0200	[thread overview]
Message-ID: <20220127081647.GB31846@intel.com> (raw)
In-Reply-To: <20220118092354.11631-3-ville.syrjala@linux.intel.com>

On Tue, Jan 18, 2022 at 11:23:41AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Extract a small helper to populate a ddb entry.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 44 +++++++++++++++++++--------------
>  1 file changed, 25 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7185af0ff205..9a9d4acb2988 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4058,6 +4058,15 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>  	return 0;
>  }
>  
> +static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
> +			      u16 start, u16 end)
> +{
> +	entry->start = start;
> +	entry->end = end;
> +
> +	return end;
> +}
> +
>  static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
>  {
>  	return INTEL_INFO(dev_priv)->dbuf.size /
> @@ -4196,8 +4205,7 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
>  	int ret;
>  
>  	if (new_dbuf_state->weight[pipe] == 0) {
> -		new_dbuf_state->ddb[pipe].start = 0;
> -		new_dbuf_state->ddb[pipe].end = 0;
> +		skl_ddb_entry_init(&new_dbuf_state->ddb[pipe], 0, 0);
>  		goto out;
>  	}
>  
> @@ -4213,8 +4221,10 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
>  	start = ddb_range_size * weight_start / weight_total;
>  	end = ddb_range_size * weight_end / weight_total;
>  
> -	new_dbuf_state->ddb[pipe].start = ddb_slices.start - mbus_offset + start;
> -	new_dbuf_state->ddb[pipe].end = ddb_slices.start - mbus_offset + end;
> +	skl_ddb_entry_init(&new_dbuf_state->ddb[pipe],
> +			   ddb_slices.start - mbus_offset + start,
> +			   ddb_slices.start - mbus_offset + end);
> +
>  out:
>  	if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] &&
>  	    skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe],
> @@ -4291,8 +4301,9 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
>  
>  static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
>  {
> -	entry->start = REG_FIELD_GET(PLANE_BUF_START_MASK, reg);
> -	entry->end = REG_FIELD_GET(PLANE_BUF_END_MASK, reg);
> +	skl_ddb_entry_init(entry,
> +			   REG_FIELD_GET(PLANE_BUF_START_MASK, reg),
> +			   REG_FIELD_GET(PLANE_BUF_END_MASK, reg));
>  	if (entry->end)
>  		entry->end++;
>  }
> @@ -5154,9 +5165,8 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  	/* Allocate fixed number of blocks for cursor. */
>  	total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
>  	alloc_size -= total[PLANE_CURSOR];
> -	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
> -		alloc->end - total[PLANE_CURSOR];
> -	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
> +	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR],
> +			   alloc->end - total[PLANE_CURSOR], alloc->end);
>  
>  	if (total_data_rate == 0)
>  		return 0;
> @@ -5257,17 +5267,13 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  			    DISPLAY_VER(dev_priv) >= 11 && uv_total[plane_id]);
>  
>  		/* Leave disabled planes at (0,0) */
> -		if (total[plane_id]) {
> -			plane_alloc->start = start;
> -			start += total[plane_id];
> -			plane_alloc->end = start;
> -		}
> +		if (total[plane_id])
> +			start = skl_ddb_entry_init(plane_alloc, start,
> +						   start + total[plane_id]);
>  
> -		if (uv_total[plane_id]) {
> -			uv_plane_alloc->start = start;
> -			start += uv_total[plane_id];
> -			uv_plane_alloc->end = start;
> -		}
> +		if (uv_total[plane_id])
> +			start = skl_ddb_entry_init(uv_plane_alloc, start,
> +						   start + uv_total[plane_id]);
>  	}
>  
>  	/*
> -- 
> 2.32.0
> 

  reply	other threads:[~2022-01-27  8:16 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-18  9:23 [Intel-gfx] [PATCH 00/15] drm/i915: Fix bandwith related cdclk calculations Ville Syrjala
2022-01-18  9:23 ` [Intel-gfx] [PATCH 01/15] drm/i915: Drop pointless dev_priv argument Ville Syrjala
2022-01-27  8:15   ` Lisovskiy, Stanislav
2022-01-18  9:23 ` [Intel-gfx] [PATCH 02/15] drm/i915: Extract skl_ddb_entry_init() Ville Syrjala
2022-01-27  8:16   ` Lisovskiy, Stanislav [this message]
2022-01-18  9:23 ` [Intel-gfx] [PATCH 03/15] drm/i915: Fix plane relative_data_rate calculation Ville Syrjala
2022-01-27  8:21   ` Lisovskiy, Stanislav
2022-01-27  8:50     ` Ville Syrjälä
2022-01-18  9:23 ` [Intel-gfx] [PATCH 04/15] drm/i915: Introduce skl_plane_ddb_iter Ville Syrjala
2022-01-27  8:22   ` Lisovskiy, Stanislav
2022-01-18  9:23 ` [Intel-gfx] [PATCH 05/15] drm/i915: Extract skl_allocate_plane_ddb() Ville Syrjala
2022-01-27  8:24   ` Lisovskiy, Stanislav
2022-01-18  9:23 ` [Intel-gfx] [PATCH 06/15] drm/i915: Extract skl_crtc_calc_dbuf_bw() Ville Syrjala
2022-01-27  8:24   ` Lisovskiy, Stanislav
2022-01-18  9:23 ` [Intel-gfx] [PATCH 07/15] drm/i915: Tweak plane ddb allocation tracking Ville Syrjala
2022-02-01  8:06   ` Lisovskiy, Stanislav
2022-01-18  9:23 ` [Intel-gfx] [PATCH 08/15] drm/i915: Split plane data_rate into data_rate+data_rate_y Ville Syrjala
2022-02-01  8:08   ` Lisovskiy, Stanislav
2022-01-18  9:23 ` [Intel-gfx] [PATCH 09/15] drm/i915: Pre-calculate plane relative data rate Ville Syrjala
2022-02-01  8:11   ` Lisovskiy, Stanislav
2022-01-18  9:23 ` [Intel-gfx] [PATCH 10/15] drm/i915: Remove total[] and uv_total[] from ddb allocation Ville Syrjala
2022-02-01  8:26   ` Lisovskiy, Stanislav
2022-01-18  9:23 ` [Intel-gfx] [PATCH 11/15] drm/i915: Nuke intel_bw_calc_min_cdclk() Ville Syrjala
2022-02-01  8:52   ` Lisovskiy, Stanislav
2022-02-01 10:05     ` Ville Syrjälä
2022-02-01 11:18       ` Lisovskiy, Stanislav
2022-02-01 13:45         ` Ville Syrjälä
2022-02-01 14:38           ` Lisovskiy, Stanislav
2022-01-18  9:23 ` [Intel-gfx] [PATCH 12/15] drm/i915: Round up when calculating display bandwidth requirements Ville Syrjala
2022-01-18  9:23 ` [Intel-gfx] [PATCH 13/15] drm/i915: Properly write lock bw_state when it changes Ville Syrjala
2022-01-18  9:23 ` [Intel-gfx] [PATCH 14/15] drm/i915: Fix DBUF bandwidth vs. cdclk handling Ville Syrjala
2022-01-18  9:23 ` [Intel-gfx] [PATCH 15/15] drm/i915: Add "maximum pipe read bandwidth" checks Ville Syrjala
2022-01-18  9:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix bandwith related cdclk calculations Patchwork
2022-01-18  9:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-01-18 10:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-18 11:32 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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