From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [CI v3 1/6] drm/i915/perf: Move OA regs to their own header
Date: Thu, 27 Jan 2022 15:43:29 -0800 [thread overview]
Message-ID: <20220127234334.4016964-2-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20220127234334.4016964-1-matthew.d.roper@intel.com>
The OA unit registers are only used by the perf code; move them to their
own header file.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gvt/scheduler.c | 1 +
drivers/gpu/drm/i915/i915_perf.c | 1 +
drivers/gpu/drm/i915/i915_perf_oa_regs.h | 497 +++++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 485 ----------------------
4 files changed, 499 insertions(+), 485 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_perf_oa_regs.h
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 42a0c9ae0a73..ecd90dbd9544 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -43,6 +43,7 @@
#include "i915_drv.h"
#include "i915_gem_gtt.h"
+#include "i915_perf_oa_regs.h"
#include "gvt.h"
#define RING_CTX_OFF(x) \
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index da4045c9df4e..20af83517cb1 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -208,6 +208,7 @@
#include "i915_drv.h"
#include "i915_perf.h"
+#include "i915_perf_oa_regs.h"
/* HW requires this to be a power of two, between 128k and 16M, though driver
* is currently generally designed assuming the largest 16M size is used such
diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
new file mode 100644
index 000000000000..5896ed43f5c4
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
@@ -0,0 +1,497 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_PERF_OA_REGS__
+#define __INTEL_PERF_OA_REGS__
+
+#include "i915_reg_defs.h"
+
+#define GEN7_OACONTROL _MMIO(0x2360)
+#define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
+#define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
+#define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6
+#define GEN7_OACONTROL_TIMER_ENABLE (1 << 5)
+#define GEN7_OACONTROL_FORMAT_A13 (0 << 2)
+#define GEN7_OACONTROL_FORMAT_A29 (1 << 2)
+#define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2)
+#define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2)
+#define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2)
+#define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2)
+#define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2)
+#define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2)
+#define GEN7_OACONTROL_FORMAT_SHIFT 2
+#define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1)
+#define GEN7_OACONTROL_ENABLE (1 << 0)
+
+#define GEN8_OACTXID _MMIO(0x2364)
+
+#define GEN8_OA_DEBUG _MMIO(0x2B04)
+#define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
+#define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
+#define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
+#define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
+
+#define GEN8_OACONTROL _MMIO(0x2B00)
+#define GEN8_OA_REPORT_FORMAT_A12 (0 << 2)
+#define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2)
+#define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2)
+#define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2)
+#define GEN8_OA_REPORT_FORMAT_SHIFT 2
+#define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1)
+#define GEN8_OA_COUNTER_ENABLE (1 << 0)
+
+#define GEN8_OACTXCONTROL _MMIO(0x2360)
+#define GEN8_OA_TIMER_PERIOD_MASK 0x3F
+#define GEN8_OA_TIMER_PERIOD_SHIFT 2
+#define GEN8_OA_TIMER_ENABLE (1 << 1)
+#define GEN8_OA_COUNTER_RESUME (1 << 0)
+
+#define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
+#define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3)
+#define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2)
+#define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1)
+#define GEN7_OABUFFER_RESUME (1 << 0)
+
+#define GEN8_OABUFFER_UDW _MMIO(0x23b4)
+#define GEN8_OABUFFER _MMIO(0x2b14)
+#define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
+
+#define GEN7_OASTATUS1 _MMIO(0x2364)
+#define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
+#define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2)
+#define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1)
+#define GEN7_OASTATUS1_REPORT_LOST (1 << 0)
+
+#define GEN7_OASTATUS2 _MMIO(0x2368)
+#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
+#define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
+
+#define GEN8_OASTATUS _MMIO(0x2b08)
+#define GEN8_OASTATUS_TAIL_POINTER_WRAP (1 << 17)
+#define GEN8_OASTATUS_HEAD_POINTER_WRAP (1 << 16)
+#define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
+#define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
+#define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1)
+#define GEN8_OASTATUS_REPORT_LOST (1 << 0)
+
+#define GEN8_OAHEADPTR _MMIO(0x2B0C)
+#define GEN8_OAHEADPTR_MASK 0xffffffc0
+#define GEN8_OATAILPTR _MMIO(0x2B10)
+#define GEN8_OATAILPTR_MASK 0xffffffc0
+
+#define OABUFFER_SIZE_128K (0 << 3)
+#define OABUFFER_SIZE_256K (1 << 3)
+#define OABUFFER_SIZE_512K (2 << 3)
+#define OABUFFER_SIZE_1M (3 << 3)
+#define OABUFFER_SIZE_2M (4 << 3)
+#define OABUFFER_SIZE_4M (5 << 3)
+#define OABUFFER_SIZE_8M (6 << 3)
+#define OABUFFER_SIZE_16M (7 << 3)
+
+#define GEN12_OA_TLB_INV_CR _MMIO(0xceec)
+
+/* Gen12 OAR unit */
+#define GEN12_OAR_OACONTROL _MMIO(0x2960)
+#define GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1
+#define GEN12_OAR_OACONTROL_COUNTER_ENABLE (1 << 0)
+
+#define GEN12_OACTXCONTROL _MMIO(0x2360)
+#define GEN12_OAR_OASTATUS _MMIO(0x2968)
+
+/* Gen12 OAG unit */
+#define GEN12_OAG_OAHEADPTR _MMIO(0xdb00)
+#define GEN12_OAG_OAHEADPTR_MASK 0xffffffc0
+#define GEN12_OAG_OATAILPTR _MMIO(0xdb04)
+#define GEN12_OAG_OATAILPTR_MASK 0xffffffc0
+
+#define GEN12_OAG_OABUFFER _MMIO(0xdb08)
+#define GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK (0x7)
+#define GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3)
+#define GEN12_OAG_OABUFFER_MEMORY_SELECT (1 << 0) /* 0: PPGTT, 1: GGTT */
+
+#define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28)
+#define GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2
+#define GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE (1 << 1)
+#define GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME (1 << 0)
+
+#define GEN12_OAG_OACONTROL _MMIO(0xdaf4)
+#define GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2
+#define GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE (1 << 0)
+
+#define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8)
+#define GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
+#define GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
+#define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
+#define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
+
+#define GEN12_OAG_OASTATUS _MMIO(0xdafc)
+#define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
+#define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1)
+#define GEN12_OAG_OASTATUS_REPORT_LOST (1 << 0)
+
+/*
+ * OA Boolean state
+ */
+
+#define OASTARTTRIG1 _MMIO(0x2710)
+#define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
+#define OASTARTTRIG1_THRESHOLD_MASK 0xffff
+
+#define OASTARTTRIG2 _MMIO(0x2714)
+#define OASTARTTRIG2_INVERT_A_0 (1 << 0)
+#define OASTARTTRIG2_INVERT_A_1 (1 << 1)
+#define OASTARTTRIG2_INVERT_A_2 (1 << 2)
+#define OASTARTTRIG2_INVERT_A_3 (1 << 3)
+#define OASTARTTRIG2_INVERT_A_4 (1 << 4)
+#define OASTARTTRIG2_INVERT_A_5 (1 << 5)
+#define OASTARTTRIG2_INVERT_A_6 (1 << 6)
+#define OASTARTTRIG2_INVERT_A_7 (1 << 7)
+#define OASTARTTRIG2_INVERT_A_8 (1 << 8)
+#define OASTARTTRIG2_INVERT_A_9 (1 << 9)
+#define OASTARTTRIG2_INVERT_A_10 (1 << 10)
+#define OASTARTTRIG2_INVERT_A_11 (1 << 11)
+#define OASTARTTRIG2_INVERT_A_12 (1 << 12)
+#define OASTARTTRIG2_INVERT_A_13 (1 << 13)
+#define OASTARTTRIG2_INVERT_A_14 (1 << 14)
+#define OASTARTTRIG2_INVERT_A_15 (1 << 15)
+#define OASTARTTRIG2_INVERT_B_0 (1 << 16)
+#define OASTARTTRIG2_INVERT_B_1 (1 << 17)
+#define OASTARTTRIG2_INVERT_B_2 (1 << 18)
+#define OASTARTTRIG2_INVERT_B_3 (1 << 19)
+#define OASTARTTRIG2_INVERT_C_0 (1 << 20)
+#define OASTARTTRIG2_INVERT_C_1 (1 << 21)
+#define OASTARTTRIG2_INVERT_D_0 (1 << 22)
+#define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23)
+#define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24)
+#define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28)
+#define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29)
+#define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30)
+#define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31)
+
+#define OASTARTTRIG3 _MMIO(0x2718)
+#define OASTARTTRIG3_NOA_SELECT_MASK 0xf
+#define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0
+#define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4
+#define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8
+#define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12
+#define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16
+#define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20
+#define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24
+#define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28
+
+#define OASTARTTRIG4 _MMIO(0x271c)
+#define OASTARTTRIG4_NOA_SELECT_MASK 0xf
+#define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0
+#define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4
+#define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8
+#define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12
+#define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16
+#define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20
+#define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24
+#define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28
+
+#define OASTARTTRIG5 _MMIO(0x2720)
+#define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
+#define OASTARTTRIG5_THRESHOLD_MASK 0xffff
+
+#define OASTARTTRIG6 _MMIO(0x2724)
+#define OASTARTTRIG6_INVERT_A_0 (1 << 0)
+#define OASTARTTRIG6_INVERT_A_1 (1 << 1)
+#define OASTARTTRIG6_INVERT_A_2 (1 << 2)
+#define OASTARTTRIG6_INVERT_A_3 (1 << 3)
+#define OASTARTTRIG6_INVERT_A_4 (1 << 4)
+#define OASTARTTRIG6_INVERT_A_5 (1 << 5)
+#define OASTARTTRIG6_INVERT_A_6 (1 << 6)
+#define OASTARTTRIG6_INVERT_A_7 (1 << 7)
+#define OASTARTTRIG6_INVERT_A_8 (1 << 8)
+#define OASTARTTRIG6_INVERT_A_9 (1 << 9)
+#define OASTARTTRIG6_INVERT_A_10 (1 << 10)
+#define OASTARTTRIG6_INVERT_A_11 (1 << 11)
+#define OASTARTTRIG6_INVERT_A_12 (1 << 12)
+#define OASTARTTRIG6_INVERT_A_13 (1 << 13)
+#define OASTARTTRIG6_INVERT_A_14 (1 << 14)
+#define OASTARTTRIG6_INVERT_A_15 (1 << 15)
+#define OASTARTTRIG6_INVERT_B_0 (1 << 16)
+#define OASTARTTRIG6_INVERT_B_1 (1 << 17)
+#define OASTARTTRIG6_INVERT_B_2 (1 << 18)
+#define OASTARTTRIG6_INVERT_B_3 (1 << 19)
+#define OASTARTTRIG6_INVERT_C_0 (1 << 20)
+#define OASTARTTRIG6_INVERT_C_1 (1 << 21)
+#define OASTARTTRIG6_INVERT_D_0 (1 << 22)
+#define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23)
+#define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24)
+#define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28)
+#define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29)
+#define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30)
+#define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31)
+
+#define OASTARTTRIG7 _MMIO(0x2728)
+#define OASTARTTRIG7_NOA_SELECT_MASK 0xf
+#define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0
+#define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4
+#define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8
+#define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12
+#define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16
+#define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20
+#define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24
+#define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28
+
+#define OASTARTTRIG8 _MMIO(0x272c)
+#define OASTARTTRIG8_NOA_SELECT_MASK 0xf
+#define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0
+#define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4
+#define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8
+#define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12
+#define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16
+#define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20
+#define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24
+#define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28
+
+#define OAREPORTTRIG1 _MMIO(0x2740)
+#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
+#define OAREPORTTRIG1_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
+
+#define OAREPORTTRIG2 _MMIO(0x2744)
+#define OAREPORTTRIG2_INVERT_A_0 (1 << 0)
+#define OAREPORTTRIG2_INVERT_A_1 (1 << 1)
+#define OAREPORTTRIG2_INVERT_A_2 (1 << 2)
+#define OAREPORTTRIG2_INVERT_A_3 (1 << 3)
+#define OAREPORTTRIG2_INVERT_A_4 (1 << 4)
+#define OAREPORTTRIG2_INVERT_A_5 (1 << 5)
+#define OAREPORTTRIG2_INVERT_A_6 (1 << 6)
+#define OAREPORTTRIG2_INVERT_A_7 (1 << 7)
+#define OAREPORTTRIG2_INVERT_A_8 (1 << 8)
+#define OAREPORTTRIG2_INVERT_A_9 (1 << 9)
+#define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
+#define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
+#define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
+#define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
+#define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
+#define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
+#define OAREPORTTRIG2_INVERT_B_0 (1 << 16)
+#define OAREPORTTRIG2_INVERT_B_1 (1 << 17)
+#define OAREPORTTRIG2_INVERT_B_2 (1 << 18)
+#define OAREPORTTRIG2_INVERT_B_3 (1 << 19)
+#define OAREPORTTRIG2_INVERT_C_0 (1 << 20)
+#define OAREPORTTRIG2_INVERT_C_1 (1 << 21)
+#define OAREPORTTRIG2_INVERT_D_0 (1 << 22)
+#define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23)
+#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
+
+#define OAREPORTTRIG3 _MMIO(0x2748)
+#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf
+#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0
+#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4
+#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8
+#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12
+#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16
+#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20
+#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24
+#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28
+
+#define OAREPORTTRIG4 _MMIO(0x274c)
+#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf
+#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0
+#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4
+#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8
+#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12
+#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16
+#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20
+#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24
+#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28
+
+#define OAREPORTTRIG5 _MMIO(0x2750)
+#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
+#define OAREPORTTRIG5_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
+
+#define OAREPORTTRIG6 _MMIO(0x2754)
+#define OAREPORTTRIG6_INVERT_A_0 (1 << 0)
+#define OAREPORTTRIG6_INVERT_A_1 (1 << 1)
+#define OAREPORTTRIG6_INVERT_A_2 (1 << 2)
+#define OAREPORTTRIG6_INVERT_A_3 (1 << 3)
+#define OAREPORTTRIG6_INVERT_A_4 (1 << 4)
+#define OAREPORTTRIG6_INVERT_A_5 (1 << 5)
+#define OAREPORTTRIG6_INVERT_A_6 (1 << 6)
+#define OAREPORTTRIG6_INVERT_A_7 (1 << 7)
+#define OAREPORTTRIG6_INVERT_A_8 (1 << 8)
+#define OAREPORTTRIG6_INVERT_A_9 (1 << 9)
+#define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
+#define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
+#define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
+#define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
+#define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
+#define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
+#define OAREPORTTRIG6_INVERT_B_0 (1 << 16)
+#define OAREPORTTRIG6_INVERT_B_1 (1 << 17)
+#define OAREPORTTRIG6_INVERT_B_2 (1 << 18)
+#define OAREPORTTRIG6_INVERT_B_3 (1 << 19)
+#define OAREPORTTRIG6_INVERT_C_0 (1 << 20)
+#define OAREPORTTRIG6_INVERT_C_1 (1 << 21)
+#define OAREPORTTRIG6_INVERT_D_0 (1 << 22)
+#define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23)
+#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
+
+#define OAREPORTTRIG7 _MMIO(0x2758)
+#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf
+#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0
+#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4
+#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8
+#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12
+#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16
+#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20
+#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24
+#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28
+
+#define OAREPORTTRIG8 _MMIO(0x275c)
+#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf
+#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0
+#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4
+#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8
+#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12
+#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16
+#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20
+#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
+#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
+
+/* Same layout as OASTARTTRIGX */
+#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
+#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
+#define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908)
+#define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c)
+#define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910)
+#define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914)
+#define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918)
+#define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c)
+
+/* Same layout as OAREPORTTRIGX */
+#define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920)
+#define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924)
+#define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928)
+#define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c)
+#define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930)
+#define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934)
+#define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938)
+#define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c)
+
+/* CECX_0 */
+#define OACEC_COMPARE_LESS_OR_EQUAL 6
+#define OACEC_COMPARE_NOT_EQUAL 5
+#define OACEC_COMPARE_LESS_THAN 4
+#define OACEC_COMPARE_GREATER_OR_EQUAL 3
+#define OACEC_COMPARE_EQUAL 2
+#define OACEC_COMPARE_GREATER_THAN 1
+#define OACEC_COMPARE_ANY_EQUAL 0
+
+#define OACEC_COMPARE_VALUE_MASK 0xffff
+#define OACEC_COMPARE_VALUE_SHIFT 3
+
+#define OACEC_SELECT_NOA (0 << 19)
+#define OACEC_SELECT_PREV (1 << 19)
+#define OACEC_SELECT_BOOLEAN (2 << 19)
+
+/* 11-bit array 0: pass-through, 1: negated */
+#define GEN12_OASCEC_NEGATE_MASK 0x7ff
+#define GEN12_OASCEC_NEGATE_SHIFT 21
+
+/* CECX_1 */
+#define OACEC_MASK_MASK 0xffff
+#define OACEC_CONSIDERATIONS_MASK 0xffff
+#define OACEC_CONSIDERATIONS_SHIFT 16
+
+#define OACEC0_0 _MMIO(0x2770)
+#define OACEC0_1 _MMIO(0x2774)
+#define OACEC1_0 _MMIO(0x2778)
+#define OACEC1_1 _MMIO(0x277c)
+#define OACEC2_0 _MMIO(0x2780)
+#define OACEC2_1 _MMIO(0x2784)
+#define OACEC3_0 _MMIO(0x2788)
+#define OACEC3_1 _MMIO(0x278c)
+#define OACEC4_0 _MMIO(0x2790)
+#define OACEC4_1 _MMIO(0x2794)
+#define OACEC5_0 _MMIO(0x2798)
+#define OACEC5_1 _MMIO(0x279c)
+#define OACEC6_0 _MMIO(0x27a0)
+#define OACEC6_1 _MMIO(0x27a4)
+#define OACEC7_0 _MMIO(0x27a8)
+#define OACEC7_1 _MMIO(0x27ac)
+
+/* Same layout as CECX_Y */
+#define GEN12_OAG_CEC0_0 _MMIO(0xd940)
+#define GEN12_OAG_CEC0_1 _MMIO(0xd944)
+#define GEN12_OAG_CEC1_0 _MMIO(0xd948)
+#define GEN12_OAG_CEC1_1 _MMIO(0xd94c)
+#define GEN12_OAG_CEC2_0 _MMIO(0xd950)
+#define GEN12_OAG_CEC2_1 _MMIO(0xd954)
+#define GEN12_OAG_CEC3_0 _MMIO(0xd958)
+#define GEN12_OAG_CEC3_1 _MMIO(0xd95c)
+#define GEN12_OAG_CEC4_0 _MMIO(0xd960)
+#define GEN12_OAG_CEC4_1 _MMIO(0xd964)
+#define GEN12_OAG_CEC5_0 _MMIO(0xd968)
+#define GEN12_OAG_CEC5_1 _MMIO(0xd96c)
+#define GEN12_OAG_CEC6_0 _MMIO(0xd970)
+#define GEN12_OAG_CEC6_1 _MMIO(0xd974)
+#define GEN12_OAG_CEC7_0 _MMIO(0xd978)
+#define GEN12_OAG_CEC7_1 _MMIO(0xd97c)
+
+/* Same layout as CECX_Y + negate 11-bit array */
+#define GEN12_OAG_SCEC0_0 _MMIO(0xdc00)
+#define GEN12_OAG_SCEC0_1 _MMIO(0xdc04)
+#define GEN12_OAG_SCEC1_0 _MMIO(0xdc08)
+#define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c)
+#define GEN12_OAG_SCEC2_0 _MMIO(0xdc10)
+#define GEN12_OAG_SCEC2_1 _MMIO(0xdc14)
+#define GEN12_OAG_SCEC3_0 _MMIO(0xdc18)
+#define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c)
+#define GEN12_OAG_SCEC4_0 _MMIO(0xdc20)
+#define GEN12_OAG_SCEC4_1 _MMIO(0xdc24)
+#define GEN12_OAG_SCEC5_0 _MMIO(0xdc28)
+#define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c)
+#define GEN12_OAG_SCEC6_0 _MMIO(0xdc30)
+#define GEN12_OAG_SCEC6_1 _MMIO(0xdc34)
+#define GEN12_OAG_SCEC7_0 _MMIO(0xdc38)
+#define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c)
+
+/* OA perf counters */
+#define OA_PERFCNT1_LO _MMIO(0x91B8)
+#define OA_PERFCNT1_HI _MMIO(0x91BC)
+#define OA_PERFCNT2_LO _MMIO(0x91C0)
+#define OA_PERFCNT2_HI _MMIO(0x91C4)
+#define OA_PERFCNT3_LO _MMIO(0x91C8)
+#define OA_PERFCNT3_HI _MMIO(0x91CC)
+#define OA_PERFCNT4_LO _MMIO(0x91D8)
+#define OA_PERFCNT4_HI _MMIO(0x91DC)
+
+#define OA_PERFMATRIX_LO _MMIO(0x91C8)
+#define OA_PERFMATRIX_HI _MMIO(0x91CC)
+
+/* NOA (HSW) */
+#define HSW_MBVID2_NOA0 _MMIO(0x9E80)
+#define HSW_MBVID2_NOA1 _MMIO(0x9E84)
+#define HSW_MBVID2_NOA2 _MMIO(0x9E88)
+#define HSW_MBVID2_NOA3 _MMIO(0x9E8C)
+#define HSW_MBVID2_NOA4 _MMIO(0x9E90)
+#define HSW_MBVID2_NOA5 _MMIO(0x9E94)
+#define HSW_MBVID2_NOA6 _MMIO(0x9E98)
+#define HSW_MBVID2_NOA7 _MMIO(0x9E9C)
+#define HSW_MBVID2_NOA8 _MMIO(0x9EA0)
+#define HSW_MBVID2_NOA9 _MMIO(0x9EA4)
+
+#define HSW_MBVID2_MISR0 _MMIO(0x9EC0)
+
+/* NOA (Gen8+) */
+#define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4)
+
+#define GEN12_OAA_DBG_REG _MMIO(0xdc44)
+#define GEN12_OAG_OA_PESS _MMIO(0x2b2c)
+#define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40)
+
+#define GDT_CHICKEN_BITS _MMIO(0x9840)
+#define GT_NOA_ENABLE 0x00000080
+
+#define NOA_DATA _MMIO(0x986C)
+#define NOA_WRITE _MMIO(0x9888)
+#define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
+
+#endif /* __INTEL_PERF_OA_REGS__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2e4dd9db63fe..b943b74f47f1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -474,132 +474,9 @@
#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
-#define GEN7_OACONTROL _MMIO(0x2360)
-#define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
-#define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
-#define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6
-#define GEN7_OACONTROL_TIMER_ENABLE (1 << 5)
-#define GEN7_OACONTROL_FORMAT_A13 (0 << 2)
-#define GEN7_OACONTROL_FORMAT_A29 (1 << 2)
-#define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2)
-#define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2)
-#define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2)
-#define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2)
-#define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2)
-#define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2)
-#define GEN7_OACONTROL_FORMAT_SHIFT 2
-#define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1)
-#define GEN7_OACONTROL_ENABLE (1 << 0)
-
-#define GEN8_OACTXID _MMIO(0x2364)
-
-#define GEN8_OA_DEBUG _MMIO(0x2B04)
-#define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
-#define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
-#define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
-#define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
-
-#define GEN8_OACONTROL _MMIO(0x2B00)
-#define GEN8_OA_REPORT_FORMAT_A12 (0 << 2)
-#define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2)
-#define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2)
-#define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2)
-#define GEN8_OA_REPORT_FORMAT_SHIFT 2
-#define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1)
-#define GEN8_OA_COUNTER_ENABLE (1 << 0)
-
-#define GEN8_OACTXCONTROL _MMIO(0x2360)
-#define GEN8_OA_TIMER_PERIOD_MASK 0x3F
-#define GEN8_OA_TIMER_PERIOD_SHIFT 2
-#define GEN8_OA_TIMER_ENABLE (1 << 1)
-#define GEN8_OA_COUNTER_RESUME (1 << 0)
-
-#define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
-#define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3)
-#define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2)
-#define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1)
-#define GEN7_OABUFFER_RESUME (1 << 0)
-
-#define GEN8_OABUFFER_UDW _MMIO(0x23b4)
-#define GEN8_OABUFFER _MMIO(0x2b14)
-#define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
-
-#define GEN7_OASTATUS1 _MMIO(0x2364)
-#define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
-#define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2)
-#define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1)
-#define GEN7_OASTATUS1_REPORT_LOST (1 << 0)
-
-#define GEN7_OASTATUS2 _MMIO(0x2368)
-#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
-#define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
-
-#define GEN8_OASTATUS _MMIO(0x2b08)
-#define GEN8_OASTATUS_TAIL_POINTER_WRAP (1 << 17)
-#define GEN8_OASTATUS_HEAD_POINTER_WRAP (1 << 16)
-#define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
-#define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
-#define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1)
-#define GEN8_OASTATUS_REPORT_LOST (1 << 0)
-
-#define GEN8_OAHEADPTR _MMIO(0x2B0C)
-#define GEN8_OAHEADPTR_MASK 0xffffffc0
-#define GEN8_OATAILPTR _MMIO(0x2B10)
-#define GEN8_OATAILPTR_MASK 0xffffffc0
-
-#define OABUFFER_SIZE_128K (0 << 3)
-#define OABUFFER_SIZE_256K (1 << 3)
-#define OABUFFER_SIZE_512K (2 << 3)
-#define OABUFFER_SIZE_1M (3 << 3)
-#define OABUFFER_SIZE_2M (4 << 3)
-#define OABUFFER_SIZE_4M (5 << 3)
-#define OABUFFER_SIZE_8M (6 << 3)
-#define OABUFFER_SIZE_16M (7 << 3)
-
-#define GEN12_OA_TLB_INV_CR _MMIO(0xceec)
-
#define GEN12_SQCM _MMIO(0x8724)
#define EN_32B_ACCESS REG_BIT(30)
-/* Gen12 OAR unit */
-#define GEN12_OAR_OACONTROL _MMIO(0x2960)
-#define GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1
-#define GEN12_OAR_OACONTROL_COUNTER_ENABLE (1 << 0)
-
-#define GEN12_OACTXCONTROL _MMIO(0x2360)
-#define GEN12_OAR_OASTATUS _MMIO(0x2968)
-
-/* Gen12 OAG unit */
-#define GEN12_OAG_OAHEADPTR _MMIO(0xdb00)
-#define GEN12_OAG_OAHEADPTR_MASK 0xffffffc0
-#define GEN12_OAG_OATAILPTR _MMIO(0xdb04)
-#define GEN12_OAG_OATAILPTR_MASK 0xffffffc0
-
-#define GEN12_OAG_OABUFFER _MMIO(0xdb08)
-#define GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK (0x7)
-#define GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3)
-#define GEN12_OAG_OABUFFER_MEMORY_SELECT (1 << 0) /* 0: PPGTT, 1: GGTT */
-
-#define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28)
-#define GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2
-#define GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE (1 << 1)
-#define GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME (1 << 0)
-
-#define GEN12_OAG_OACONTROL _MMIO(0xdaf4)
-#define GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2
-#define GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE (1 << 0)
-
-#define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8)
-#define GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
-#define GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
-#define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
-#define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
-
-#define GEN12_OAG_OASTATUS _MMIO(0xdafc)
-#define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
-#define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1)
-#define GEN12_OAG_OASTATUS_REPORT_LOST (1 << 0)
-
/*
* Flexible, Aggregate EU Counter Registers.
* Note: these aren't contiguous
@@ -615,341 +492,6 @@
#define RT_CTRL _MMIO(0xe530)
#define DIS_NULL_QUERY REG_BIT(10)
-/*
- * OA Boolean state
- */
-
-#define OASTARTTRIG1 _MMIO(0x2710)
-#define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
-#define OASTARTTRIG1_THRESHOLD_MASK 0xffff
-
-#define OASTARTTRIG2 _MMIO(0x2714)
-#define OASTARTTRIG2_INVERT_A_0 (1 << 0)
-#define OASTARTTRIG2_INVERT_A_1 (1 << 1)
-#define OASTARTTRIG2_INVERT_A_2 (1 << 2)
-#define OASTARTTRIG2_INVERT_A_3 (1 << 3)
-#define OASTARTTRIG2_INVERT_A_4 (1 << 4)
-#define OASTARTTRIG2_INVERT_A_5 (1 << 5)
-#define OASTARTTRIG2_INVERT_A_6 (1 << 6)
-#define OASTARTTRIG2_INVERT_A_7 (1 << 7)
-#define OASTARTTRIG2_INVERT_A_8 (1 << 8)
-#define OASTARTTRIG2_INVERT_A_9 (1 << 9)
-#define OASTARTTRIG2_INVERT_A_10 (1 << 10)
-#define OASTARTTRIG2_INVERT_A_11 (1 << 11)
-#define OASTARTTRIG2_INVERT_A_12 (1 << 12)
-#define OASTARTTRIG2_INVERT_A_13 (1 << 13)
-#define OASTARTTRIG2_INVERT_A_14 (1 << 14)
-#define OASTARTTRIG2_INVERT_A_15 (1 << 15)
-#define OASTARTTRIG2_INVERT_B_0 (1 << 16)
-#define OASTARTTRIG2_INVERT_B_1 (1 << 17)
-#define OASTARTTRIG2_INVERT_B_2 (1 << 18)
-#define OASTARTTRIG2_INVERT_B_3 (1 << 19)
-#define OASTARTTRIG2_INVERT_C_0 (1 << 20)
-#define OASTARTTRIG2_INVERT_C_1 (1 << 21)
-#define OASTARTTRIG2_INVERT_D_0 (1 << 22)
-#define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23)
-#define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24)
-#define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28)
-#define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29)
-#define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30)
-#define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31)
-
-#define OASTARTTRIG3 _MMIO(0x2718)
-#define OASTARTTRIG3_NOA_SELECT_MASK 0xf
-#define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0
-#define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4
-#define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8
-#define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12
-#define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16
-#define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20
-#define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24
-#define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28
-
-#define OASTARTTRIG4 _MMIO(0x271c)
-#define OASTARTTRIG4_NOA_SELECT_MASK 0xf
-#define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0
-#define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4
-#define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8
-#define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12
-#define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16
-#define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20
-#define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24
-#define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28
-
-#define OASTARTTRIG5 _MMIO(0x2720)
-#define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
-#define OASTARTTRIG5_THRESHOLD_MASK 0xffff
-
-#define OASTARTTRIG6 _MMIO(0x2724)
-#define OASTARTTRIG6_INVERT_A_0 (1 << 0)
-#define OASTARTTRIG6_INVERT_A_1 (1 << 1)
-#define OASTARTTRIG6_INVERT_A_2 (1 << 2)
-#define OASTARTTRIG6_INVERT_A_3 (1 << 3)
-#define OASTARTTRIG6_INVERT_A_4 (1 << 4)
-#define OASTARTTRIG6_INVERT_A_5 (1 << 5)
-#define OASTARTTRIG6_INVERT_A_6 (1 << 6)
-#define OASTARTTRIG6_INVERT_A_7 (1 << 7)
-#define OASTARTTRIG6_INVERT_A_8 (1 << 8)
-#define OASTARTTRIG6_INVERT_A_9 (1 << 9)
-#define OASTARTTRIG6_INVERT_A_10 (1 << 10)
-#define OASTARTTRIG6_INVERT_A_11 (1 << 11)
-#define OASTARTTRIG6_INVERT_A_12 (1 << 12)
-#define OASTARTTRIG6_INVERT_A_13 (1 << 13)
-#define OASTARTTRIG6_INVERT_A_14 (1 << 14)
-#define OASTARTTRIG6_INVERT_A_15 (1 << 15)
-#define OASTARTTRIG6_INVERT_B_0 (1 << 16)
-#define OASTARTTRIG6_INVERT_B_1 (1 << 17)
-#define OASTARTTRIG6_INVERT_B_2 (1 << 18)
-#define OASTARTTRIG6_INVERT_B_3 (1 << 19)
-#define OASTARTTRIG6_INVERT_C_0 (1 << 20)
-#define OASTARTTRIG6_INVERT_C_1 (1 << 21)
-#define OASTARTTRIG6_INVERT_D_0 (1 << 22)
-#define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23)
-#define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24)
-#define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28)
-#define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29)
-#define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30)
-#define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31)
-
-#define OASTARTTRIG7 _MMIO(0x2728)
-#define OASTARTTRIG7_NOA_SELECT_MASK 0xf
-#define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0
-#define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4
-#define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8
-#define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12
-#define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16
-#define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20
-#define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24
-#define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28
-
-#define OASTARTTRIG8 _MMIO(0x272c)
-#define OASTARTTRIG8_NOA_SELECT_MASK 0xf
-#define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0
-#define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4
-#define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8
-#define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12
-#define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16
-#define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20
-#define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24
-#define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28
-
-#define OAREPORTTRIG1 _MMIO(0x2740)
-#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
-#define OAREPORTTRIG1_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
-
-#define OAREPORTTRIG2 _MMIO(0x2744)
-#define OAREPORTTRIG2_INVERT_A_0 (1 << 0)
-#define OAREPORTTRIG2_INVERT_A_1 (1 << 1)
-#define OAREPORTTRIG2_INVERT_A_2 (1 << 2)
-#define OAREPORTTRIG2_INVERT_A_3 (1 << 3)
-#define OAREPORTTRIG2_INVERT_A_4 (1 << 4)
-#define OAREPORTTRIG2_INVERT_A_5 (1 << 5)
-#define OAREPORTTRIG2_INVERT_A_6 (1 << 6)
-#define OAREPORTTRIG2_INVERT_A_7 (1 << 7)
-#define OAREPORTTRIG2_INVERT_A_8 (1 << 8)
-#define OAREPORTTRIG2_INVERT_A_9 (1 << 9)
-#define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
-#define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
-#define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
-#define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
-#define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
-#define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
-#define OAREPORTTRIG2_INVERT_B_0 (1 << 16)
-#define OAREPORTTRIG2_INVERT_B_1 (1 << 17)
-#define OAREPORTTRIG2_INVERT_B_2 (1 << 18)
-#define OAREPORTTRIG2_INVERT_B_3 (1 << 19)
-#define OAREPORTTRIG2_INVERT_C_0 (1 << 20)
-#define OAREPORTTRIG2_INVERT_C_1 (1 << 21)
-#define OAREPORTTRIG2_INVERT_D_0 (1 << 22)
-#define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23)
-#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
-
-#define OAREPORTTRIG3 _MMIO(0x2748)
-#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf
-#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0
-#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4
-#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8
-#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12
-#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16
-#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20
-#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24
-#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28
-
-#define OAREPORTTRIG4 _MMIO(0x274c)
-#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf
-#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0
-#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4
-#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8
-#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12
-#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16
-#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20
-#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24
-#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28
-
-#define OAREPORTTRIG5 _MMIO(0x2750)
-#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
-#define OAREPORTTRIG5_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
-
-#define OAREPORTTRIG6 _MMIO(0x2754)
-#define OAREPORTTRIG6_INVERT_A_0 (1 << 0)
-#define OAREPORTTRIG6_INVERT_A_1 (1 << 1)
-#define OAREPORTTRIG6_INVERT_A_2 (1 << 2)
-#define OAREPORTTRIG6_INVERT_A_3 (1 << 3)
-#define OAREPORTTRIG6_INVERT_A_4 (1 << 4)
-#define OAREPORTTRIG6_INVERT_A_5 (1 << 5)
-#define OAREPORTTRIG6_INVERT_A_6 (1 << 6)
-#define OAREPORTTRIG6_INVERT_A_7 (1 << 7)
-#define OAREPORTTRIG6_INVERT_A_8 (1 << 8)
-#define OAREPORTTRIG6_INVERT_A_9 (1 << 9)
-#define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
-#define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
-#define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
-#define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
-#define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
-#define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
-#define OAREPORTTRIG6_INVERT_B_0 (1 << 16)
-#define OAREPORTTRIG6_INVERT_B_1 (1 << 17)
-#define OAREPORTTRIG6_INVERT_B_2 (1 << 18)
-#define OAREPORTTRIG6_INVERT_B_3 (1 << 19)
-#define OAREPORTTRIG6_INVERT_C_0 (1 << 20)
-#define OAREPORTTRIG6_INVERT_C_1 (1 << 21)
-#define OAREPORTTRIG6_INVERT_D_0 (1 << 22)
-#define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23)
-#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
-
-#define OAREPORTTRIG7 _MMIO(0x2758)
-#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf
-#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0
-#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4
-#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8
-#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12
-#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16
-#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20
-#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24
-#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28
-
-#define OAREPORTTRIG8 _MMIO(0x275c)
-#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf
-#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0
-#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4
-#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8
-#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12
-#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16
-#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20
-#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
-#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
-
-/* Same layout as OASTARTTRIGX */
-#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
-#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
-#define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908)
-#define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c)
-#define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910)
-#define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914)
-#define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918)
-#define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c)
-
-/* Same layout as OAREPORTTRIGX */
-#define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920)
-#define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924)
-#define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928)
-#define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c)
-#define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930)
-#define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934)
-#define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938)
-#define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c)
-
-/* CECX_0 */
-#define OACEC_COMPARE_LESS_OR_EQUAL 6
-#define OACEC_COMPARE_NOT_EQUAL 5
-#define OACEC_COMPARE_LESS_THAN 4
-#define OACEC_COMPARE_GREATER_OR_EQUAL 3
-#define OACEC_COMPARE_EQUAL 2
-#define OACEC_COMPARE_GREATER_THAN 1
-#define OACEC_COMPARE_ANY_EQUAL 0
-
-#define OACEC_COMPARE_VALUE_MASK 0xffff
-#define OACEC_COMPARE_VALUE_SHIFT 3
-
-#define OACEC_SELECT_NOA (0 << 19)
-#define OACEC_SELECT_PREV (1 << 19)
-#define OACEC_SELECT_BOOLEAN (2 << 19)
-
-/* 11-bit array 0: pass-through, 1: negated */
-#define GEN12_OASCEC_NEGATE_MASK 0x7ff
-#define GEN12_OASCEC_NEGATE_SHIFT 21
-
-/* CECX_1 */
-#define OACEC_MASK_MASK 0xffff
-#define OACEC_CONSIDERATIONS_MASK 0xffff
-#define OACEC_CONSIDERATIONS_SHIFT 16
-
-#define OACEC0_0 _MMIO(0x2770)
-#define OACEC0_1 _MMIO(0x2774)
-#define OACEC1_0 _MMIO(0x2778)
-#define OACEC1_1 _MMIO(0x277c)
-#define OACEC2_0 _MMIO(0x2780)
-#define OACEC2_1 _MMIO(0x2784)
-#define OACEC3_0 _MMIO(0x2788)
-#define OACEC3_1 _MMIO(0x278c)
-#define OACEC4_0 _MMIO(0x2790)
-#define OACEC4_1 _MMIO(0x2794)
-#define OACEC5_0 _MMIO(0x2798)
-#define OACEC5_1 _MMIO(0x279c)
-#define OACEC6_0 _MMIO(0x27a0)
-#define OACEC6_1 _MMIO(0x27a4)
-#define OACEC7_0 _MMIO(0x27a8)
-#define OACEC7_1 _MMIO(0x27ac)
-
-/* Same layout as CECX_Y */
-#define GEN12_OAG_CEC0_0 _MMIO(0xd940)
-#define GEN12_OAG_CEC0_1 _MMIO(0xd944)
-#define GEN12_OAG_CEC1_0 _MMIO(0xd948)
-#define GEN12_OAG_CEC1_1 _MMIO(0xd94c)
-#define GEN12_OAG_CEC2_0 _MMIO(0xd950)
-#define GEN12_OAG_CEC2_1 _MMIO(0xd954)
-#define GEN12_OAG_CEC3_0 _MMIO(0xd958)
-#define GEN12_OAG_CEC3_1 _MMIO(0xd95c)
-#define GEN12_OAG_CEC4_0 _MMIO(0xd960)
-#define GEN12_OAG_CEC4_1 _MMIO(0xd964)
-#define GEN12_OAG_CEC5_0 _MMIO(0xd968)
-#define GEN12_OAG_CEC5_1 _MMIO(0xd96c)
-#define GEN12_OAG_CEC6_0 _MMIO(0xd970)
-#define GEN12_OAG_CEC6_1 _MMIO(0xd974)
-#define GEN12_OAG_CEC7_0 _MMIO(0xd978)
-#define GEN12_OAG_CEC7_1 _MMIO(0xd97c)
-
-/* Same layout as CECX_Y + negate 11-bit array */
-#define GEN12_OAG_SCEC0_0 _MMIO(0xdc00)
-#define GEN12_OAG_SCEC0_1 _MMIO(0xdc04)
-#define GEN12_OAG_SCEC1_0 _MMIO(0xdc08)
-#define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c)
-#define GEN12_OAG_SCEC2_0 _MMIO(0xdc10)
-#define GEN12_OAG_SCEC2_1 _MMIO(0xdc14)
-#define GEN12_OAG_SCEC3_0 _MMIO(0xdc18)
-#define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c)
-#define GEN12_OAG_SCEC4_0 _MMIO(0xdc20)
-#define GEN12_OAG_SCEC4_1 _MMIO(0xdc24)
-#define GEN12_OAG_SCEC5_0 _MMIO(0xdc28)
-#define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c)
-#define GEN12_OAG_SCEC6_0 _MMIO(0xdc30)
-#define GEN12_OAG_SCEC6_1 _MMIO(0xdc34)
-#define GEN12_OAG_SCEC7_0 _MMIO(0xdc38)
-#define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c)
-
-/* OA perf counters */
-#define OA_PERFCNT1_LO _MMIO(0x91B8)
-#define OA_PERFCNT1_HI _MMIO(0x91BC)
-#define OA_PERFCNT2_LO _MMIO(0x91C0)
-#define OA_PERFCNT2_HI _MMIO(0x91C4)
-#define OA_PERFCNT3_LO _MMIO(0x91C8)
-#define OA_PERFCNT3_HI _MMIO(0x91CC)
-#define OA_PERFCNT4_LO _MMIO(0x91D8)
-#define OA_PERFCNT4_HI _MMIO(0x91DC)
-
-#define OA_PERFMATRIX_LO _MMIO(0x91C8)
-#define OA_PERFMATRIX_HI _MMIO(0x91CC)
-
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 _MMIO(0x0D00)
#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
@@ -979,23 +521,6 @@
/* RCP unit config (Gen8+) */
#define RCP_CONFIG _MMIO(0x0D08)
-/* NOA (HSW) */
-#define HSW_MBVID2_NOA0 _MMIO(0x9E80)
-#define HSW_MBVID2_NOA1 _MMIO(0x9E84)
-#define HSW_MBVID2_NOA2 _MMIO(0x9E88)
-#define HSW_MBVID2_NOA3 _MMIO(0x9E8C)
-#define HSW_MBVID2_NOA4 _MMIO(0x9E90)
-#define HSW_MBVID2_NOA5 _MMIO(0x9E94)
-#define HSW_MBVID2_NOA6 _MMIO(0x9E98)
-#define HSW_MBVID2_NOA7 _MMIO(0x9E9C)
-#define HSW_MBVID2_NOA8 _MMIO(0x9EA0)
-#define HSW_MBVID2_NOA9 _MMIO(0x9EA4)
-
-#define HSW_MBVID2_MISR0 _MMIO(0x9EC0)
-
-/* NOA (Gen8+) */
-#define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4)
-
#define MICRO_BP0_0 _MMIO(0x9800)
#define MICRO_BP0_2 _MMIO(0x9804)
#define MICRO_BP0_1 _MMIO(0x9808)
@@ -1017,16 +542,6 @@
#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
#define MICRO_BP_FIRED_ARMED _MMIO(0x983C)
-#define GEN12_OAA_DBG_REG _MMIO(0xdc44)
-#define GEN12_OAG_OA_PESS _MMIO(0x2b2c)
-#define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40)
-
-#define GDT_CHICKEN_BITS _MMIO(0x9840)
-#define GT_NOA_ENABLE 0x00000080
-
-#define NOA_DATA _MMIO(0x986C)
-#define NOA_WRITE _MMIO(0x9888)
-#define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
--
2.34.1
next prev parent reply other threads:[~2022-01-27 23:43 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-27 23:43 [Intel-gfx] [CI v3 0/6] Second round of i915_reg.h splitting Matt Roper
2022-01-27 23:43 ` Matt Roper [this message]
2022-01-27 23:43 ` [Intel-gfx] [CI v3 2/6] drm/i915/perf: Express OA register ranges with i915_range Matt Roper
2022-01-27 23:43 ` [Intel-gfx] [CI v3 3/6] drm/i915: Parameterize R_PWR_CLK_STATE register definition Matt Roper
2022-01-27 23:43 ` [Intel-gfx] [CI v3 4/6] drm/i915: Parameterize MI_PREDICATE registers Matt Roper
2022-01-27 23:43 ` [Intel-gfx] [CI v3 5/6] drm/i915: Move GT registers to their own header file Matt Roper
2022-01-27 23:43 ` [Intel-gfx] [CI v3 6/6] drm/i915: Only include i915_reg.h from .c files Matt Roper
2022-01-28 2:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Second round of i915_reg.h splitting (rev3) Patchwork
2022-01-28 2:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-01-28 2:44 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-28 8:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-01-28 15:21 ` Matt Roper
2022-01-28 15:49 ` Tvrtko Ursulin
2022-01-28 16:07 ` Maarten Lankhorst
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