From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3DA42CA1 for ; Mon, 31 Jan 2022 19:34:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643657699; x=1675193699; h=date:from:to:cc:subject:message-id:mime-version; bh=cChH8+znn3t0kReebLQbywe4khYSpVp1da+Pn8uCcTo=; b=Y0ZvV+Wv2Xh9vxrn32grjmnsUSOn02aPTeNODuk0cs54JAqYRjFVph5+ 4/IRRuU+EGoEyt5wS6Il6oW4kX1OwUO0xR+KcuJcTJPSb6ggyaJKeOtq3 iICX8mod7ENfgg9dcE0kh2O/1vHunskVZzZ3bsV3r15GzPOG522FCHJre V0PumxIFqwrKvxLPy64S0dE8hdHJEglr4oIN2ld5nMg1WiCzLlOH2syfI iJBje0/bHtFQraTPmcgxNSI/nOrxuiTPJSxu49iL46N+JMwrKwYEIrwXj BVudBOr4UYPNxZVomErzuE4IawC5nLtHJaoCmBGvgZ6HE9r9cNyYjFlrw g==; X-IronPort-AV: E=McAfee;i="6200,9189,10244"; a="245127925" X-IronPort-AV: E=Sophos;i="5.88,331,1635231600"; d="scan'208";a="245127925" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2022 11:34:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,331,1635231600"; d="scan'208";a="675836719" Received: from lkp-server01.sh.intel.com (HELO 276f1b88eecb) ([10.239.97.150]) by fmsmga001.fm.intel.com with ESMTP; 31 Jan 2022 11:34:45 -0800 Received: from kbuild by 276f1b88eecb with local (Exim 4.92) (envelope-from ) id 1nEcRo-000SHh-D0; Mon, 31 Jan 2022 19:34:44 +0000 Date: Tue, 1 Feb 2022 03:34:12 +0800 From: kernel test robot To: Tom Cc: llvm@lists.linux.dev, kbuild-all@lists.01.org, linux-kernel@vger.kernel.org, Emil Renner Berthing Subject: [esmil:visionfive 29/62] drivers/soc/sifive/sifive_l2_cache.c:152:3: error: implicit declaration of function 'writeq' Message-ID: <202202010337.bSdnhIBF-lkp@intel.com> Precedence: bulk X-Mailing-List: llvm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.10.1 (2018-07-13) tree: https://github.com/esmil/linux visionfive head: 8c758048edfd830baceb991167131c9d55786544 commit: 601a2f4e945153ebae8645596eda50ea39369c88 [29/62] sifive/sifive_l2_cache: Add sifive_l2_flush64_range function config: riscv-randconfig-r004-20220130 (https://download.01.org/0day-ci/archive/20220201/202202010337.bSdnhIBF-lkp@intel.com/config) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 2cdbaca3943a4d6259119f185656328bd3805b68) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install riscv cross compiling tool for clang build # apt-get install binutils-riscv64-linux-gnu # https://github.com/esmil/linux/commit/601a2f4e945153ebae8645596eda50ea39369c88 git remote add esmil https://github.com/esmil/linux git fetch --no-tags esmil visionfive git checkout 601a2f4e945153ebae8645596eda50ea39369c88 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): >> drivers/soc/sifive/sifive_l2_cache.c:152:3: error: implicit declaration of function 'writeq' [-Werror,-Wimplicit-function-declaration] writeq(line, l2_base + SIFIVE_L2_FLUSH64); ^ drivers/soc/sifive/sifive_l2_cache.c:142:19: warning: result of comparison of constant 36507222016 with expression of type 'unsigned long' is always false [-Wtautological-constant-out-of-range-compare] (start + len) > (CONFIG_SIFIVE_L2_FLUSH_START + ~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1 warning and 1 error generated. vim +/writeq +152 drivers/soc/sifive/sifive_l2_cache.c 123 124 #ifdef CONFIG_SIFIVE_L2_FLUSH 125 void sifive_l2_flush64_range(unsigned long start, unsigned long len) 126 { 127 unsigned long line; 128 129 if(!l2_base) { 130 pr_warn("L2CACHE: base addr invalid, skipping flush\n"); 131 return; 132 } 133 134 /* TODO: if (len == 0), skipping flush or going on? */ 135 if(!len) { 136 pr_debug("L2CACHE: flush64 range @ 0x%lx(len:0)\n", start); 137 return; 138 } 139 140 /* make sure the address is in the range */ 141 if(start < CONFIG_SIFIVE_L2_FLUSH_START || 142 (start + len) > (CONFIG_SIFIVE_L2_FLUSH_START + 143 CONFIG_SIFIVE_L2_FLUSH_SIZE)) { 144 pr_warn("L2CACHE: flush64 out of range: %lx(%lx), skip flush\n", 145 start, len); 146 return; 147 } 148 149 mb(); /* sync */ 150 for (line = start; line < start + len; 151 line += SIFIVE_L2_FLUSH64_LINE_LEN) { > 152 writeq(line, l2_base + SIFIVE_L2_FLUSH64); 153 mb(); 154 } 155 } 156 EXPORT_SYMBOL_GPL(sifive_l2_flush64_range); 157 #endif 158 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: multipart/mixed; boundary="===============7763176135395541894==" MIME-Version: 1.0 From: kernel test robot To: kbuild-all@lists.01.org Subject: [esmil:visionfive 29/62] drivers/soc/sifive/sifive_l2_cache.c:152:3: error: implicit declaration of function 'writeq' Date: Tue, 01 Feb 2022 03:34:12 +0800 Message-ID: <202202010337.bSdnhIBF-lkp@intel.com> List-Id: --===============7763176135395541894== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable tree: https://github.com/esmil/linux visionfive head: 8c758048edfd830baceb991167131c9d55786544 commit: 601a2f4e945153ebae8645596eda50ea39369c88 [29/62] sifive/sifive_l2_c= ache: Add sifive_l2_flush64_range function config: riscv-randconfig-r004-20220130 (https://download.01.org/0day-ci/arc= hive/20220201/202202010337.bSdnhIBF-lkp(a)intel.com/config) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 2cdbac= a3943a4d6259119f185656328bd3805b68) reproduce (this is a W=3D1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/= make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install riscv cross compiling tool for clang build # apt-get install binutils-riscv64-linux-gnu # https://github.com/esmil/linux/commit/601a2f4e945153ebae8645596ed= a50ea39369c88 git remote add esmil https://github.com/esmil/linux git fetch --no-tags esmil visionfive git checkout 601a2f4e945153ebae8645596eda50ea39369c88 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=3D$HOME/0day COMPILER=3Dclang make.cross W=3D= 1 O=3Dbuild_dir ARCH=3Driscv SHELL=3D/bin/bash If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): >> drivers/soc/sifive/sifive_l2_cache.c:152:3: error: implicit declaration = of function 'writeq' [-Werror,-Wimplicit-function-declaration] writeq(line, l2_base + SIFIVE_L2_FLUSH64); ^ drivers/soc/sifive/sifive_l2_cache.c:142:19: warning: result of comparis= on of constant 36507222016 with expression of type 'unsigned long' is alway= s false [-Wtautological-constant-out-of-range-compare] (start + len) > (CONFIG_SIFIVE_L2_FLUSH_START + ~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1 warning and 1 error generated. vim +/writeq +152 drivers/soc/sifive/sifive_l2_cache.c 123 = 124 #ifdef CONFIG_SIFIVE_L2_FLUSH 125 void sifive_l2_flush64_range(unsigned long start, unsigned long len) 126 { 127 unsigned long line; 128 = 129 if(!l2_base) { 130 pr_warn("L2CACHE: base addr invalid, skipping flush\n"); 131 return; 132 } 133 = 134 /* TODO: if (len =3D=3D 0), skipping flush or going on? */ 135 if(!len) { 136 pr_debug("L2CACHE: flush64 range @ 0x%lx(len:0)\n", start); 137 return; 138 } 139 = 140 /* make sure the address is in the range */ 141 if(start < CONFIG_SIFIVE_L2_FLUSH_START || 142 (start + len) > (CONFIG_SIFIVE_L2_FLUSH_START + 143 CONFIG_SIFIVE_L2_FLUSH_SIZE)) { 144 pr_warn("L2CACHE: flush64 out of range: %lx(%lx), skip flush\n", 145 start, len); 146 return; 147 } 148 = 149 mb(); /* sync */ 150 for (line =3D start; line < start + len; 151 line +=3D SIFIVE_L2_FLUSH64_LINE_LEN) { > 152 writeq(line, l2_base + SIFIVE_L2_FLUSH64); 153 mb(); 154 } 155 } 156 EXPORT_SYMBOL_GPL(sifive_l2_flush64_range); 157 #endif 158 = --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org --===============7763176135395541894==--