From: Taniya Das <tdas@codeaurora.org>
To: "Stephen Boyd" <sboyd@kernel.org>,
"Michael Turquette " <mturquette@baylibre.com>
Cc: Rajendra Nayak <rnayak@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
Taniya Das <tdas@codeaurora.org>
Subject: [PATCH v1 4/4] clk: qcom: sc7280: Update clk_init_data to const for clock controllers
Date: Thu, 3 Feb 2022 00:05:28 +0530 [thread overview]
Message-ID: <20220202183528.3911-4-tdas@codeaurora.org> (raw)
In-Reply-To: <20220202183528.3911-1-tdas@codeaurora.org>
Update clk_init_data to const and also use index instead of fw_name for
graphics, lpasscc and video clock controller.
Fixes: 3e0f01d6c7e74 ("clk: qcom: Add graphics clock controller driver for SC7280")
Fixes: 4ab43d171181d ("clk: qcom: Add lpass clock controller driver for SC7280")
Fixes: fae7617bb1428 ("clk: qcom: Add video clock controller driver for SC7280")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
drivers/clk/qcom/gpucc-sc7280.c | 56 +++++++++++++++----------------
drivers/clk/qcom/lpasscc-sc7280.c | 14 ++++----
drivers/clk/qcom/videocc-sc7280.c | 26 +++++++-------
3 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c
index 9a832f2bcf49..e8f6abc5261f 100644
--- a/drivers/clk/qcom/gpucc-sc7280.c
+++ b/drivers/clk/qcom/gpucc-sc7280.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021-2022, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
@@ -36,10 +36,10 @@ static struct clk_alpha_pll gpu_cc_pll0 = {
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "gpu_cc_pll0",
.parent_data = &(const struct clk_parent_data){
- .fw_name = "bi_tcxo",
+ .index = 0,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
@@ -65,10 +65,10 @@ static struct clk_alpha_pll gpu_cc_pll1 = {
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
- .fw_name = "bi_tcxo",
+ .index = 0,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
@@ -85,11 +85,11 @@ static const struct parent_map gpu_cc_parent_map_0[] = {
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
- { .fw_name = "bi_tcxo" },
+ { .index = 0 },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
- { .fw_name = "gcc_gpu_gpll0_clk_src" },
- { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
+ { .index = 1 }, /* gcc_gpu_gpll0_clk_src */
+ { .index = 2 }, /* gcc_gpu_gpll0_div_clk_src */
};
static const struct parent_map gpu_cc_parent_map_1[] = {
@@ -100,10 +100,10 @@ static const struct parent_map gpu_cc_parent_map_1[] = {
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
- { .fw_name = "bi_tcxo", },
+ { .index = 0, },
{ .hw = &gpu_cc_pll1.clkr.hw },
- { .fw_name = "gcc_gpu_gpll0_clk_src", },
- { .fw_name = "gcc_gpu_gpll0_div_clk_src", },
+ { .index = 1 }, /* gcc_gpu_gpll0_clk_src */
+ { .index = 2 }, /* gcc_gpu_gpll0_div_clk_src */
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
@@ -119,7 +119,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
+ .clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
@@ -140,7 +140,7 @@ static struct clk_rcg2 gpu_cc_hub_clk_src = {
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
+ .clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
@@ -152,7 +152,7 @@ static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
.reg = 0x11c0,
.shift = 0,
.width = 4,
- .clkr.hw.init = &(struct clk_init_data) {
+ .clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_ahb_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
@@ -167,7 +167,7 @@ static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
.reg = 0x11bc,
.shift = 0,
.width = 4,
- .clkr.hw.init = &(struct clk_init_data) {
+ .clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_cx_int_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
@@ -184,7 +184,7 @@ static struct clk_branch gpu_cc_ahb_clk = {
.clkr = {
.enable_reg = 0x1078,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
@@ -202,7 +202,7 @@ static struct clk_branch gpu_cc_crc_ahb_clk = {
.clkr = {
.enable_reg = 0x107c,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
@@ -220,7 +220,7 @@ static struct clk_branch gpu_cc_cx_gmu_clk = {
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
@@ -238,7 +238,7 @@ static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.clkr = {
.enable_reg = 0x108c,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.ops = &clk_branch2_ops,
},
@@ -251,7 +251,7 @@ static struct clk_branch gpu_cc_cxo_aon_clk = {
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.ops = &clk_branch2_ops,
},
@@ -264,7 +264,7 @@ static struct clk_branch gpu_cc_cxo_clk = {
.clkr = {
.enable_reg = 0x109c,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cxo_clk",
.ops = &clk_branch2_aon_ops,
},
@@ -277,7 +277,7 @@ static struct clk_branch gpu_cc_gx_gmu_clk = {
.clkr = {
.enable_reg = 0x1064,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "gpu_cc_gx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
@@ -295,7 +295,7 @@ static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.clkr = {
.enable_reg = 0x5000,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.ops = &clk_branch2_ops,
},
@@ -308,7 +308,7 @@ static struct clk_branch gpu_cc_hub_aon_clk = {
.clkr = {
.enable_reg = 0x1178,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_aon_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
@@ -326,7 +326,7 @@ static struct clk_branch gpu_cc_hub_cx_int_clk = {
.clkr = {
.enable_reg = 0x1204,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_cx_int_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
@@ -344,7 +344,7 @@ static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
.clkr = {
.enable_reg = 0x802c,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "gpu_cc_mnd1x_0_gfx3d_clk",
.ops = &clk_branch2_ops,
},
@@ -357,7 +357,7 @@ static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
.clkr = {
.enable_reg = 0x8030,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "gpu_cc_mnd1x_1_gfx3d_clk",
.ops = &clk_branch2_ops,
},
@@ -370,7 +370,7 @@ static struct clk_branch gpu_cc_sleep_clk = {
.clkr = {
.enable_reg = 0x1090,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c
index b39ee1c9647b..ef055706b442 100644
--- a/drivers/clk/qcom/lpasscc-sc7280.c
+++ b/drivers/clk/qcom/lpasscc-sc7280.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021-2022, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
@@ -23,7 +23,7 @@ static struct clk_branch lpass_q6ss_ahbm_clk = {
.clkr = {
.enable_reg = 0x1c,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "lpass_q6ss_ahbm_clk",
.ops = &clk_branch2_ops,
},
@@ -36,7 +36,7 @@ static struct clk_branch lpass_q6ss_ahbs_clk = {
.clkr = {
.enable_reg = 0x20,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "lpass_q6ss_ahbs_clk",
.ops = &clk_branch2_ops,
},
@@ -49,7 +49,7 @@ static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
.clkr = {
.enable_reg = 0x0,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "lpass_top_cc_lpi_q6_axim_hs_clk",
.ops = &clk_branch2_ops,
},
@@ -63,7 +63,7 @@ static struct clk_branch lpass_qdsp6ss_core_clk = {
.clkr = {
.enable_reg = 0x20,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "lpass_qdsp6ss_core_clk",
.ops = &clk_branch2_ops,
},
@@ -77,7 +77,7 @@ static struct clk_branch lpass_qdsp6ss_xo_clk = {
.clkr = {
.enable_reg = 0x38,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "lpass_qdsp6ss_xo_clk",
.ops = &clk_branch2_ops,
},
@@ -91,7 +91,7 @@ static struct clk_branch lpass_qdsp6ss_sleep_clk = {
.clkr = {
.enable_reg = 0x3c,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "lpass_qdsp6ss_sleep_clk",
.ops = &clk_branch2_ops,
},
diff --git a/drivers/clk/qcom/videocc-sc7280.c b/drivers/clk/qcom/videocc-sc7280.c
index 615695d82319..ba192ce6163e 100644
--- a/drivers/clk/qcom/videocc-sc7280.c
+++ b/drivers/clk/qcom/videocc-sc7280.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021-2022, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
@@ -45,10 +45,10 @@ static struct clk_alpha_pll video_pll0 = {
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "video_pll0",
.parent_data = &(const struct clk_parent_data){
- .fw_name = "bi_tcxo",
+ .index = 0,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
@@ -62,7 +62,7 @@ static const struct parent_map video_cc_parent_map_0[] = {
};
static const struct clk_parent_data video_cc_parent_data_0[] = {
- { .fw_name = "bi_tcxo" },
+ { .index = 0 },
{ .hw = &video_pll0.clkr.hw },
};
@@ -89,7 +89,7 @@ static struct clk_rcg2 video_cc_iris_clk_src = {
.hid_width = 5,
.parent_map = video_cc_parent_map_0,
.freq_tbl = ftbl_video_cc_iris_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
+ .clkr.hw.init = &(const struct clk_init_data){
.name = "video_cc_iris_clk_src",
.parent_data = video_cc_parent_data_0,
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
@@ -109,7 +109,7 @@ static struct clk_rcg2 video_cc_sleep_clk_src = {
.hid_width = 5,
.parent_map = video_cc_parent_map_1,
.freq_tbl = ftbl_video_cc_sleep_clk_src,
- .clkr.hw.init = &(struct clk_init_data){
+ .clkr.hw.init = &(const struct clk_init_data){
.name = "video_cc_sleep_clk_src",
.parent_data = video_cc_parent_data_1,
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
@@ -123,7 +123,7 @@ static struct clk_branch video_cc_iris_ahb_clk = {
.clkr = {
.enable_reg = 0x5004,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "video_cc_iris_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_iris_clk_src.clkr.hw,
@@ -141,7 +141,7 @@ static struct clk_branch video_cc_mvs0_axi_clk = {
.clkr = {
.enable_reg = 0x800c,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "video_cc_mvs0_axi_clk",
.ops = &clk_branch2_ops,
},
@@ -156,7 +156,7 @@ static struct clk_branch video_cc_mvs0_core_clk = {
.clkr = {
.enable_reg = 0x3010,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "video_cc_mvs0_core_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_iris_clk_src.clkr.hw,
@@ -174,7 +174,7 @@ static struct clk_branch video_cc_mvsc_core_clk = {
.clkr = {
.enable_reg = 0x2014,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "video_cc_mvsc_core_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_iris_clk_src.clkr.hw,
@@ -192,7 +192,7 @@ static struct clk_branch video_cc_mvsc_ctl_axi_clk = {
.clkr = {
.enable_reg = 0x8004,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "video_cc_mvsc_ctl_axi_clk",
.ops = &clk_branch2_ops,
},
@@ -205,7 +205,7 @@ static struct clk_branch video_cc_sleep_clk = {
.clkr = {
.enable_reg = 0x7034,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "video_cc_sleep_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_sleep_clk_src.clkr.hw,
@@ -223,7 +223,7 @@ static struct clk_branch video_cc_venus_ahb_clk = {
.clkr = {
.enable_reg = 0x801c,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
+ .hw.init = &(const struct clk_init_data){
.name = "video_cc_venus_ahb_clk",
.ops = &clk_branch2_ops,
},
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
next prev parent reply other threads:[~2022-02-02 18:36 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-02 18:35 [PATCH v1 1/4] clk: qcom: sc7280: Update clk_init_data to const for GCC Taniya Das
2022-02-02 18:35 ` [PATCH v1 2/4] clk: qcom: sc7280: Update clk_init_data to const for CAMCC Taniya Das
2022-02-02 18:35 ` [PATCH v1 3/4] clk: qcom: sc7280: Update clk_init_data to const for DISPCC Taniya Das
2022-02-02 18:35 ` Taniya Das [this message]
2022-02-17 22:44 ` [PATCH v1 1/4] clk: qcom: sc7280: Update clk_init_data to const for GCC Stephen Boyd
2022-06-24 17:08 ` Bjorn Andersson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220202183528.3911-4-tdas@codeaurora.org \
--to=tdas@codeaurora.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-soc@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=rnayak@codeaurora.org \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.