diff for duplicates of <20220210054947.170134-8-apatel@ventanamicro.com> diff --git a/a/1.txt b/N1/1.txt index 279a85a..f7e1a5d 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -221,7 +221,7 @@ index 52bce5dbb11f..95506ffb816c 100644 + #size-cells = <0>; + #address-cells = <1>; + -+ cpu at 0 { ++ cpu@0 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x0>; @@ -237,7 +237,7 @@ index 52bce5dbb11f..95506ffb816c 100644 + }; + }; + -+ cpu at 1 { ++ cpu@1 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x1>; @@ -253,7 +253,7 @@ index 52bce5dbb11f..95506ffb816c 100644 + }; + }; + -+ cpu at 10 { ++ cpu@10 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x10>; @@ -269,7 +269,7 @@ index 52bce5dbb11f..95506ffb816c 100644 + }; + }; + -+ cpu at 11 { ++ cpu@11 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x11>; diff --git a/a/content_digest b/N1/content_digest index 2816409..76035f8 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,7 +2,28 @@ "From\0Anup Patel <apatel@ventanamicro.com>\0" "Subject\0[PATCH v11 7/8] dt-bindings: Add common bindings for ARM and RISC-V idle states\0" "Date\0Thu, 10 Feb 2022 11:19:46 +0530\0" - "To\0kvm-riscv@lists.infradead.org\0" + "To\0Palmer Dabbelt <palmer@dabbelt.com>" + Paul Walmsley <paul.walmsley@sifive.com> + Albert Ou <aou@eecs.berkeley.edu> + Daniel Lezcano <daniel.lezcano@linaro.org> + Ulf Hansson <ulf.hansson@linaro.org> + Rafael J . Wysocki <rjw@rjwysocki.net> + Pavel Machek <pavel@ucw.cz> + " Rob Herring <robh+dt@kernel.org>\0" + "Cc\0Sandeep Tripathy <milun.tripathy@gmail.com>" + Atish Patra <atishp@atishpatra.org> + Alistair Francis <Alistair.Francis@wdc.com> + Liush <liush@allwinnertech.com> + Anup Patel <anup@brainfault.org> + devicetree@vger.kernel.org + linux-riscv@lists.infradead.org + linux-kernel@vger.kernel.org + linux-pm@vger.kernel.org + linux-arm-kernel@lists.infradead.org + kvm-riscv@lists.infradead.org + Anup Patel <apatel@ventanamicro.com> + Rob Herring <robh@kernel.org> + " Guo Ren <guoren@kernel.org>\0" "\00:1\0" "b\0" "From: Anup Patel <anup.patel@wdc.com>\n" @@ -228,7 +249,7 @@ "+ #size-cells = <0>;\n" "+ #address-cells = <1>;\n" "+\n" - "+ cpu at 0 {\n" + "+ cpu@0 {\n" "+ device_type = \"cpu\";\n" "+ compatible = \"riscv\";\n" "+ reg = <0x0>;\n" @@ -244,7 +265,7 @@ "+ };\n" "+ };\n" "+\n" - "+ cpu at 1 {\n" + "+ cpu@1 {\n" "+ device_type = \"cpu\";\n" "+ compatible = \"riscv\";\n" "+ reg = <0x1>;\n" @@ -260,7 +281,7 @@ "+ };\n" "+ };\n" "+\n" - "+ cpu at 10 {\n" + "+ cpu@10 {\n" "+ device_type = \"cpu\";\n" "+ compatible = \"riscv\";\n" "+ reg = <0x10>;\n" @@ -276,7 +297,7 @@ "+ };\n" "+ };\n" "+\n" - "+ cpu at 11 {\n" + "+ cpu@11 {\n" "+ device_type = \"cpu\";\n" "+ compatible = \"riscv\";\n" "+ reg = <0x11>;\n" @@ -388,4 +409,4 @@ "-- \n" 2.25.1 -9d86d8654ac24e9fa42d4db7403a2ecccc47fe36a68c8718b2bd133c366d85aa +2c3757dc665df53d6c81fa7abf62414fcec36d7cf693dcb486b6669b22a6841c
diff --git a/a/1.txt b/N2/1.txt index 279a85a..21a9be4 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -221,7 +221,7 @@ index 52bce5dbb11f..95506ffb816c 100644 + #size-cells = <0>; + #address-cells = <1>; + -+ cpu at 0 { ++ cpu@0 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x0>; @@ -237,7 +237,7 @@ index 52bce5dbb11f..95506ffb816c 100644 + }; + }; + -+ cpu at 1 { ++ cpu@1 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x1>; @@ -253,7 +253,7 @@ index 52bce5dbb11f..95506ffb816c 100644 + }; + }; + -+ cpu at 10 { ++ cpu@10 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x10>; @@ -269,7 +269,7 @@ index 52bce5dbb11f..95506ffb816c 100644 + }; + }; + -+ cpu at 11 { ++ cpu@11 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x11>; @@ -380,3 +380,9 @@ index aa5fb64d57eb..f62f646bc695 100644 - interrupt-controller -- 2.25.1 + + +_______________________________________________ +linux-riscv mailing list +linux-riscv@lists.infradead.org +http://lists.infradead.org/mailman/listinfo/linux-riscv diff --git a/a/content_digest b/N2/content_digest index 2816409..04cc807 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -2,7 +2,28 @@ "From\0Anup Patel <apatel@ventanamicro.com>\0" "Subject\0[PATCH v11 7/8] dt-bindings: Add common bindings for ARM and RISC-V idle states\0" "Date\0Thu, 10 Feb 2022 11:19:46 +0530\0" - "To\0kvm-riscv@lists.infradead.org\0" + "To\0Palmer Dabbelt <palmer@dabbelt.com>" + Paul Walmsley <paul.walmsley@sifive.com> + Albert Ou <aou@eecs.berkeley.edu> + Daniel Lezcano <daniel.lezcano@linaro.org> + Ulf Hansson <ulf.hansson@linaro.org> + Rafael J . Wysocki <rjw@rjwysocki.net> + Pavel Machek <pavel@ucw.cz> + " Rob Herring <robh+dt@kernel.org>\0" + "Cc\0Sandeep Tripathy <milun.tripathy@gmail.com>" + Atish Patra <atishp@atishpatra.org> + Alistair Francis <Alistair.Francis@wdc.com> + Liush <liush@allwinnertech.com> + Anup Patel <anup@brainfault.org> + devicetree@vger.kernel.org + linux-riscv@lists.infradead.org + linux-kernel@vger.kernel.org + linux-pm@vger.kernel.org + linux-arm-kernel@lists.infradead.org + kvm-riscv@lists.infradead.org + Anup Patel <apatel@ventanamicro.com> + Rob Herring <robh@kernel.org> + " Guo Ren <guoren@kernel.org>\0" "\00:1\0" "b\0" "From: Anup Patel <anup.patel@wdc.com>\n" @@ -228,7 +249,7 @@ "+ #size-cells = <0>;\n" "+ #address-cells = <1>;\n" "+\n" - "+ cpu at 0 {\n" + "+ cpu@0 {\n" "+ device_type = \"cpu\";\n" "+ compatible = \"riscv\";\n" "+ reg = <0x0>;\n" @@ -244,7 +265,7 @@ "+ };\n" "+ };\n" "+\n" - "+ cpu at 1 {\n" + "+ cpu@1 {\n" "+ device_type = \"cpu\";\n" "+ compatible = \"riscv\";\n" "+ reg = <0x1>;\n" @@ -260,7 +281,7 @@ "+ };\n" "+ };\n" "+\n" - "+ cpu at 10 {\n" + "+ cpu@10 {\n" "+ device_type = \"cpu\";\n" "+ compatible = \"riscv\";\n" "+ reg = <0x10>;\n" @@ -276,7 +297,7 @@ "+ };\n" "+ };\n" "+\n" - "+ cpu at 11 {\n" + "+ cpu@11 {\n" "+ device_type = \"cpu\";\n" "+ compatible = \"riscv\";\n" "+ reg = <0x11>;\n" @@ -386,6 +407,12 @@ " - riscv,isa\n" " - interrupt-controller\n" "-- \n" - 2.25.1 + "2.25.1\n" + "\n" + "\n" + "_______________________________________________\n" + "linux-riscv mailing list\n" + "linux-riscv@lists.infradead.org\n" + http://lists.infradead.org/mailman/listinfo/linux-riscv -9d86d8654ac24e9fa42d4db7403a2ecccc47fe36a68c8718b2bd133c366d85aa +e3ee12f4e153fcb73d1f80d1da84506e37c7a82dd62c97a815323cff6695c49c
diff --git a/a/1.txt b/N3/1.txt index 279a85a..23097e0 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -221,7 +221,7 @@ index 52bce5dbb11f..95506ffb816c 100644 + #size-cells = <0>; + #address-cells = <1>; + -+ cpu at 0 { ++ cpu@0 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x0>; @@ -237,7 +237,7 @@ index 52bce5dbb11f..95506ffb816c 100644 + }; + }; + -+ cpu at 1 { ++ cpu@1 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x1>; @@ -253,7 +253,7 @@ index 52bce5dbb11f..95506ffb816c 100644 + }; + }; + -+ cpu at 10 { ++ cpu@10 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x10>; @@ -269,7 +269,7 @@ index 52bce5dbb11f..95506ffb816c 100644 + }; + }; + -+ cpu at 11 { ++ cpu@11 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x11>; @@ -380,3 +380,9 @@ index aa5fb64d57eb..f62f646bc695 100644 - interrupt-controller -- 2.25.1 + + +_______________________________________________ +linux-arm-kernel mailing list +linux-arm-kernel@lists.infradead.org +http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/a/content_digest b/N3/content_digest index 2816409..2a7fef2 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -2,7 +2,28 @@ "From\0Anup Patel <apatel@ventanamicro.com>\0" "Subject\0[PATCH v11 7/8] dt-bindings: Add common bindings for ARM and RISC-V idle states\0" "Date\0Thu, 10 Feb 2022 11:19:46 +0530\0" - "To\0kvm-riscv@lists.infradead.org\0" + "To\0Palmer Dabbelt <palmer@dabbelt.com>" + Paul Walmsley <paul.walmsley@sifive.com> + Albert Ou <aou@eecs.berkeley.edu> + Daniel Lezcano <daniel.lezcano@linaro.org> + Ulf Hansson <ulf.hansson@linaro.org> + Rafael J . Wysocki <rjw@rjwysocki.net> + Pavel Machek <pavel@ucw.cz> + " Rob Herring <robh+dt@kernel.org>\0" + "Cc\0Sandeep Tripathy <milun.tripathy@gmail.com>" + Atish Patra <atishp@atishpatra.org> + Alistair Francis <Alistair.Francis@wdc.com> + Liush <liush@allwinnertech.com> + Anup Patel <anup@brainfault.org> + devicetree@vger.kernel.org + linux-riscv@lists.infradead.org + linux-kernel@vger.kernel.org + linux-pm@vger.kernel.org + linux-arm-kernel@lists.infradead.org + kvm-riscv@lists.infradead.org + Anup Patel <apatel@ventanamicro.com> + Rob Herring <robh@kernel.org> + " Guo Ren <guoren@kernel.org>\0" "\00:1\0" "b\0" "From: Anup Patel <anup.patel@wdc.com>\n" @@ -228,7 +249,7 @@ "+ #size-cells = <0>;\n" "+ #address-cells = <1>;\n" "+\n" - "+ cpu at 0 {\n" + "+ cpu@0 {\n" "+ device_type = \"cpu\";\n" "+ compatible = \"riscv\";\n" "+ reg = <0x0>;\n" @@ -244,7 +265,7 @@ "+ };\n" "+ };\n" "+\n" - "+ cpu at 1 {\n" + "+ cpu@1 {\n" "+ device_type = \"cpu\";\n" "+ compatible = \"riscv\";\n" "+ reg = <0x1>;\n" @@ -260,7 +281,7 @@ "+ };\n" "+ };\n" "+\n" - "+ cpu at 10 {\n" + "+ cpu@10 {\n" "+ device_type = \"cpu\";\n" "+ compatible = \"riscv\";\n" "+ reg = <0x10>;\n" @@ -276,7 +297,7 @@ "+ };\n" "+ };\n" "+\n" - "+ cpu at 11 {\n" + "+ cpu@11 {\n" "+ device_type = \"cpu\";\n" "+ compatible = \"riscv\";\n" "+ reg = <0x11>;\n" @@ -386,6 +407,12 @@ " - riscv,isa\n" " - interrupt-controller\n" "-- \n" - 2.25.1 + "2.25.1\n" + "\n" + "\n" + "_______________________________________________\n" + "linux-arm-kernel mailing list\n" + "linux-arm-kernel@lists.infradead.org\n" + http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -9d86d8654ac24e9fa42d4db7403a2ecccc47fe36a68c8718b2bd133c366d85aa +b858707f06d543264ae329567459991b2e6ff730735b51272d821762f76de588
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