From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Rohit Agarwal <quic_rohiagar@quicinc.com>
Cc: agross@kernel.org, bjorn.andersson@linaro.org,
mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/8] dt-bindings: clock: Add A7 PLL binding for SDX65
Date: Mon, 14 Feb 2022 14:05:34 +0530 [thread overview]
Message-ID: <20220214083534.GC3494@thinkpad> (raw)
In-Reply-To: <1644821869-27199-1-git-send-email-quic_rohiagar@quicinc.com>
On Mon, Feb 14, 2022 at 12:27:49PM +0530, Rohit Agarwal wrote:
> Add YAML binding for Cortex A7 PLL clock in Qualcomm
> platforms like SDX65.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> ---
> Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
> index 8666e99..b8889dc 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
> @@ -10,13 +10,14 @@ maintainers:
> - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>
> description:
> - The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
> + The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
> frequency clock to the CPU.
>
> properties:
> compatible:
> enum:
> - qcom,sdx55-a7pll
> + - qcom,sdx65-a7pll
>
> reg:
> maxItems: 1
> --
> 2.7.4
>
prev parent reply other threads:[~2022-02-14 8:35 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-14 6:57 [PATCH 3/8] dt-bindings: clock: Add A7 PLL binding for SDX65 Rohit Agarwal
2022-02-14 8:35 ` Manivannan Sadhasivam [this message]
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