From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C046C433F5 for ; Mon, 14 Feb 2022 10:31:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347948AbiBNKbk (ORCPT ); Mon, 14 Feb 2022 05:31:40 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:41532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348114AbiBNKaq (ORCPT ); Mon, 14 Feb 2022 05:30:46 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 511169BF59; Mon, 14 Feb 2022 01:59:20 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D347760921; Mon, 14 Feb 2022 09:59:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A0ADEC340E9; Mon, 14 Feb 2022 09:59:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1644832757; bh=QUTNVwz+yVHcljh6bmE8p4c9DR9JYaIcZoW8VimMowk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nbbT5LjaKP8tVo2f5y5eDjga3J39Sb1+HhpgVR/Oxp99qM9PR/hju42F1SXEnodl+ G4RsRGndicu2DwOED+dK7rUz/zo8gOnezpO805ssTi28fL3RO8NgMJYwObylsMi2Og C3IndlSZH/zNJI9TtdFDTgWwiTpqos6kDw865I14= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Mark Brown , Catalin Marinas , Sasha Levin Subject: [PATCH 5.16 107/203] arm64: Enable Cortex-A510 erratum 2051678 by default Date: Mon, 14 Feb 2022 10:25:51 +0100 Message-Id: <20220214092513.882562722@linuxfoundation.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220214092510.221474733@linuxfoundation.org> References: <20220214092510.221474733@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mark Brown [ Upstream commit a4b92cebc31d49b7e6ef0ce584c7f2a2e112877d ] The recently added configuration option for Cortex A510 erratum 2051678 does not have a "default y" unlike other errata fixes. This appears to simply be an oversight since the help text suggests enabling the option if unsure and there's nothing in the commit log to suggest it is intentional. Fixes: 297ae1eb23b0 ("arm64: cpufeature: List early Cortex-A510 parts as having broken dbm") Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20220201144838.20037-1-broonie@kernel.org Signed-off-by: Catalin Marinas Signed-off-by: Sasha Levin --- arch/arm64/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 38e7f19df14d4..ae0e93871ee5f 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -672,6 +672,7 @@ config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE config ARM64_ERRATUM_2051678 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" + default y help This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. Affected Coretex-A510 might not respect the ordering rules for -- 2.34.1