From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 93097C433FE for ; Tue, 15 Feb 2022 17:37:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sTaVug6X2GtZOSunQneumCAOOQmrNLCTCev3Gy8lW2s=; b=rXYIo1PQRqHS+S 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id D4A8C1F44CBE; Tue, 15 Feb 2022 17:37:08 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1644946629; bh=VpNusZYmXQK6qGrjf8z92Hd+sj83I7JkS+WLoKjOZNQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=B1YSrd/uGp+OJTVYWQm7EHo/2JYu1Vpe62A10UXnm04MVw3sTmcgPdWnBbt4gqeFc i01FlJ9swPPPKi837EbZ2XwSnu/je29TINoCxYN4SqZv6rs7w+HLcvy74pfWO3cBuY 8GzXJMA+DvwUQeLTCl9L0PsbmdsntYR3R+hfVjxJAKZLyW8SIlVygA5MoehxLAzwXw S4zFWiTqENxM7l+uyzNzRMekXQ4iuY7CvUCcxLMhr1pHv3EbJXI4ue1bWBu/FJgute xBaDCNL1Biu29KlptJsG16m4gfnAyuoqWuOfTTICvMRS08pVFDOCCITFTdEQc6TG56 wLp+qoz0fcusw== Date: Tue, 15 Feb 2022 18:37:05 +0100 From: Boris Brezillon To: Apurva Nandan Cc: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Patrice Chotard , Christophe Kerello , Daniel Palmer , Alexander Lobakin , , , , Subject: Re: [PATCH v3 05/17] mtd: spinand: Define ctrl_ops for non-page read/write op templates Message-ID: <20220215183705.574df0c1@collabora.com> In-Reply-To: References: <20220101074250.14443-1-a-nandan@ti.com> <20220101074250.14443-6-a-nandan@ti.com> <20220103110107.45594e78@collabora.com> Organization: Collabora X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.31; x86_64-redhat-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220215_093713_508165_E1A07B7A X-CRM114-Status: GOOD ( 42.21 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org SGkgQXB1cnZhLAoKT24gVHVlLCAxNSBGZWIgMjAyMiAyMTowMzo1MiArMDUzMApBcHVydmEgTmFu ZGFuIDxhLW5hbmRhbkB0aS5jb20+IHdyb3RlOgoKPiBIaSBCb3JpcywKPiAKPiBPbiAwMy8wMS8y MiAxNTozMSwgQm9yaXMgQnJlemlsbG9uIHdyb3RlOgo+ID4gT24gU2F0LCAxIEphbiAyMDIyIDEz OjEyOjM4ICswNTMwCj4gPiBBcHVydmEgTmFuZGFuIDxhLW5hbmRhbkB0aS5jb20+IHdyb3RlOgo+ ID4gIAo+ID4+ICdjdHJsX29wcycgYXJlIG9wIHRlbXBsYXRlcyBmb3Igbm9uLXBhZ2UgcmVhZC93 cml0ZSBvcGVyYXRpb25zLAo+ID4+IHdoaWNoIGFyZTogcmVzZXQsIGdldF9mZWF0dXJlLCBzZXRf ZmVhdHVyZSwgd3JpdGVfZW5hYmxlLCBibG9ja19lcmFzZSwKPiA+PiBwYWdlX3JlYWQgYW5kIHBy b2dyYW1fZXhlY3V0ZSBvcHMuIFRoZSAnY3RybF9vcHMnIHN0cnVjdCBjb250YWlucyBpbiBpdAo+ ID4+IG9wIHRlbXBsYXRlcyBmb3IgZWFjaCBvZiB0aGlzIG9wLCBhcyB3ZWxsIGFzIGVudW0gc3Bp bmFuZF9wcm90b2NvbAo+ID4+IGRlbm90aW5nIHByb3RvY29sIG9mIGFsbCB0aGVzZSBvcHMuCj4g Pj4KPiA+PiBXZSByZXF1aXJlIHRoZXNlIG5ldyBvcCB0ZW1wbGF0ZXMgYmVjYXVzZSBvZiBkZXZp YXRpb24gaW4gc3RhbmRhcmQKPiA+PiBTUElOQU5EIG9wcyBieSBtYW51ZmFjdHVyZXJzIGFuZCBh bHNvIGR1ZSB0byBjaGFuZ2VzIHdoZW4gdGhlcmUgaXMgYQo+ID4+IGNoYW5nZSBpbiBTUEkgcHJv dG9jb2wvbW9kZS4gVGhpcyBwcmV2ZW50cyB0aGUgY29yZSBmcm9tIGxpdmUtcGF0Y2hpbmcKPiA+ PiBhbmQgdmVuZG9yLXNwZWNpZmljIGFkanVzdG1lbnRzIGluIG9wcy4KPiA+Pgo+ID4+IERlZmlu ZSAnY3RybF9vcHMnLCBhZGQgbWFjcm9zIHRvIGluaXRpYWxpemUgaXQgYW5kIGFkZCBpdCBpbgo+ ID4+IHNwaW5hbmRfZGV2aWNlLgo+ID4+Cj4gPj4gU2lnbmVkLW9mZi1ieTogQXB1cnZhIE5hbmRh biA8YS1uYW5kYW5AdGkuY29tPgo+ID4+IC0tLQo+ID4+ICAgaW5jbHVkZS9saW51eC9tdGQvc3Bp bmFuZC5oIHwgMzMgKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrCj4gPj4gICAxIGZp bGUgY2hhbmdlZCwgMzMgaW5zZXJ0aW9ucygrKQo+ID4+Cj4gPj4gZGlmZiAtLWdpdCBhL2luY2x1 ZGUvbGludXgvbXRkL3NwaW5hbmQuaCBiL2luY2x1ZGUvbGludXgvbXRkL3NwaW5hbmQuaAo+ID4+ IGluZGV4IDQzOWQ4Y2U0MGUxZC4uZTVkZjYyMjBlYzFlIDEwMDY0NAo+ID4+IC0tLSBhL2luY2x1 ZGUvbGludXgvbXRkL3NwaW5hbmQuaAo+ID4+ICsrKyBiL2luY2x1ZGUvbGludXgvbXRkL3NwaW5h bmQuaAo+ID4+IEBAIC0zNTYsNiArMzU2LDM1IEBAIHN0cnVjdCBzcGluYW5kX29wX3ZhcmlhbnRz IHsKPiA+PiAgIAkJCXNpemVvZihzdHJ1Y3Qgc3BpX21lbV9vcCksCQkJXAo+ID4+ICAgCX0KPiA+ PiAgIAo+ID4+ICtzdHJ1Y3Qgc3BpbmFuZF9jdHJsX29wcyB7Cj4gPj4gKwljb25zdCBzdHJ1Y3Qg ewo+ID4+ICsJCXN0cnVjdCBzcGlfbWVtX29wIHJlc2V0Owo+ID4+ICsJCXN0cnVjdCBzcGlfbWVt X29wIGdldF9mZWF0dXJlOwo+ID4+ICsJCXN0cnVjdCBzcGlfbWVtX29wIHNldF9mZWF0dXJlOwo+ ID4+ICsJCXN0cnVjdCBzcGlfbWVtX29wIHdyaXRlX2VuYWJsZTsKPiA+PiArCQlzdHJ1Y3Qgc3Bp X21lbV9vcCBibG9ja19lcmFzZTsKPiA+PiArCQlzdHJ1Y3Qgc3BpX21lbV9vcCBwYWdlX3JlYWQ7 Cj4gPj4gKwkJc3RydWN0IHNwaV9tZW1fb3AgcHJvZ3JhbV9leGVjdXRlOwo+ID4+ICsJfSBvcHM7 Cj4gPj4gKwljb25zdCBlbnVtIHNwaW5hbmRfcHJvdG9jb2wgcHJvdG9jb2w7ICAKPiA+IERvIHlv dSByZWFsbHkgbmVlZCB0aGF0IHByb3RvY29sIGZpZWxkPwo+ID4gIAo+ID4+ICt9Owo+ID4+ICsK PiA+PiArI2RlZmluZSBTUElOQU5EX0NUUkxfT1BTKF9fcHJvdG9jb2wsIF9fcmVzZXQsIF9fZ2V0 X2ZlYXR1cmUsIF9fc2V0X2ZlYXR1cmUsCVwKPiA+PiArCQkJIF9fd3JpdGVfZW5hYmxlLCBfX2Js b2NrX2VyYXNlLCBfX3BhZ2VfcmVhZCwJCVwKPiA+PiArCQkJIF9fcHJvZ3JhbV9leGVjdXRlKQkJ CQkJXAo+ID4+ICsJewkJCQkJCQkJCVwKPiA+PiArCQkub3BzID0gewkJCQkJCQlcCj4gPj4gKwkJ CS5yZXNldCA9IF9fcmVzZXQsCQkJCQlcCj4gPj4gKwkJCS5nZXRfZmVhdHVyZSA9IF9fZ2V0X2Zl YXR1cmUsCQkJCVwKPiA+PiArCQkJLnNldF9mZWF0dXJlID0gX19zZXRfZmVhdHVyZSwJCQkJXAo+ ID4+ICsJCQkud3JpdGVfZW5hYmxlID0gX193cml0ZV9lbmFibGUsCQkJCVwKPiA+PiArCQkJLmJs b2NrX2VyYXNlID0gX19ibG9ja19lcmFzZSwJCQkJXAo+ID4+ICsJCQkucGFnZV9yZWFkID0gX19w YWdlX3JlYWQsCQkJCVwKPiA+PiArCQkJLnByb2dyYW1fZXhlY3V0ZSA9IF9fcHJvZ3JhbV9leGVj dXRlLAkJCVwKPiA+PiArCQl9LAkJCQkJCQkJXAo+ID4+ICsJCS5wcm90b2NvbCA9IF9fcHJvdG9j b2wsCQkJCQkJXAo+ID4+ICsJfQo+ID4+ICsKPiA+PiAgIC8qKgo+ID4+ICAgICogc3BpbmFuZF9l Y2NfaW5mbyAtIGRlc2NyaXB0aW9uIG9mIHRoZSBvbi1kaWUgRUNDIGltcGxlbWVudGVkIGJ5IGEg U1BJIE5BTkQKPiA+PiAgICAqCQkgICAgICBjaGlwCj4gPj4gQEAgLTQ2OCw2ICs0OTcsOCBAQCBz dHJ1Y3Qgc3BpbmFuZF9kaXJtYXAgewo+ID4+ICAgICogQGRhdGFfb3BzLnJlYWRfY2FjaGU6IHJl YWQgY2FjaGUgb3AgdGVtcGxhdGUKPiA+PiAgICAqIEBkYXRhX29wcy53cml0ZV9jYWNoZTogd3Jp dGUgY2FjaGUgb3AgdGVtcGxhdGUKPiA+PiAgICAqIEBkYXRhX29wcy51cGRhdGVfY2FjaGU6IHVw ZGF0ZSBjYWNoZSBvcCB0ZW1wbGF0ZQo+ID4+ICsgKiBAY3RybF9vcHM6IHZhcmlvdXMgU1BJIG1l bSBvcCB0ZW1wbGF0ZXMgZm9yIGhhbmRsaW5nIHRoZSBmbGFzaCBkZXZpY2UsIGkuZS4KPiA+PiAr ICoJICAgICAgbm9uIHBhZ2UtcmVhZC93cml0ZSBvcHMuCj4gPj4gICAgKiBAc2VsZWN0X3Rhcmdl dDogc2VsZWN0IGEgc3BlY2lmaWMgdGFyZ2V0L2RpZS4gVXN1YWxseSBjYWxsZWQgYmVmb3JlIHNl bmRpbmcKPiA+PiAgICAqCQkgICBhIGNvbW1hbmQgYWRkcmVzc2luZyBhIHBhZ2Ugb3IgYW4gZXJh c2VibG9jayBlbWJlZGRlZCBpbgo+ID4+ICAgICoJCSAgIHRoaXMgZGllLiBPbmx5IHJlcXVpcmVk IGlmIHlvdXIgY2hpcCBleHBvc2VzIHNldmVyYWwgZGllcwo+ID4+IEBAIC00OTgsNiArNTI5LDgg QEAgc3RydWN0IHNwaW5hbmRfZGV2aWNlIHsKPiA+PiAgIAkJY29uc3Qgc3RydWN0IHNwaV9tZW1f b3AgKnVwZGF0ZV9jYWNoZTsKPiA+PiAgIAl9IGRhdGFfb3BzOwo+ID4+ICAgCj4gPj4gKwljb25z dCBzdHJ1Y3Qgc3BpbmFuZF9jdHJsX29wcyAqY3RybF9vcHM7Cj4gPj4gKyAgCj4gPiBPa2F5LCBJ IGhhZCBzb21ldGhpbmcgc2xpZ2h0bHkgZGlmZmVyZW50IGluIG1pbmQuIEZpcnN0LCBJJ2QgcHV0 IGFsbAo+ID4gdGVtcGxhdGVzIGluIGEgc3RydWN0Ogo+ID4KPiA+IHN0cnVjdCBzcGluYW5kX29w X3RlbXBsYXRlcyB7Cj4gPiAJY29uc3Qgc3RydWN0IHNwaV9tZW1fb3AgKnJlYWRfY2FjaGU7Cj4g PiAJY29uc3Qgc3RydWN0IHNwaV9tZW1fb3AgKndyaXRlX2NhY2hlOwo+ID4gCWNvbnN0IHN0cnVj dCBzcGlfbWVtX29wICp1cGRhdGVfY2FjaGU7Cj4gPiAJY29uc3Qgc3RydWN0IHNwaV9tZW1fb3Ag KnJlc2V0Owo+ID4gCWNvbnN0IHN0cnVjdCBzcGlfbWVtX29wICpnZXRfZmVhdHVyZTsKPiA+IAlj b25zdCBzdHJ1Y3Qgc3BpX21lbV9vcCAqc2V0X2ZlYXR1cmU7Cj4gPiAJY29uc3Qgc3RydWN0IHNw aV9tZW1fb3AgKndyaXRlX2VuYWJsZTsKPiA+IAljb25zdCBzdHJ1Y3Qgc3BpX21lbV9vcCAqYmxv Y2tfZXJhc2U7Cj4gPiAJY29uc3Qgc3RydWN0IHNwaV9tZW1fb3AgKnBhZ2VfbG9hZDsKPiA+IAlj b25zdCBzdHJ1Y3Qgc3BpX21lbV9vcCAqcHJvZ3JhbV9leGVjdXRlOwo+ID4gfTsKPiA+Cj4gPiBU aGVuLCBhdCB0aGUgc3BpbmFuZCBsZXZlbCwgSSdkIGRlZmluZSBhbiBhcnJheSBvZiB0ZW1wbGF0 ZXM6Cj4gPgo+ID4gZW51bSBzcGluYW5kX3Byb3RvY29sIHsKPiA+IAlTUElOQU5EXzFTXzFTXzFT LAo+ID4gCVNQSU5BTkRfMlNfMlNfMlMsCj4gPiAJU1BJTkFORF80U180U180UywKPiA+IAlTUElO QU5EXzhTXzhTXzhTLAo+ID4gCVNQSU5BTkRfOERfOERfOEQsCj4gPiAJU1BJTkFORF9OVU1fUFJP VE9DT0xTLAo+ID4gfTsKPiA+Cj4gPiBzdHJ1Y3Qgc3BpbmFuZF9kZXZpY2Ugewo+ID4gCS4uLgo+ ID4gCWVudW0gc3BpbmFuZF9wcm90b2NvbCBwcm90b2NvbDsKPiA+IAljb25zdCBzdHJ1Y3Qgc3Bp bmFuZF9vcF90ZW1wbGF0ZXMgKm9wX3RlbXBsYXRlc1tTUElOQU5EX05VTV9QUk9UT0NPTFNdOwoK SXQgc2hvdWxkIHByb2JhYmx5IGJlCgoJc3RydWN0IHNwaW5hbmRfb3BfdGVtcGxhdGVzIG9wX3Rl bXBsYXRlc1tTUElOQU5EX05VTV9QUk9UT0NPTFNdOwoKd2l0aCB0aGUgc3BpbmFuZF9vcF90ZW1w bGF0ZXMgc3RydWN0IGRlZmluZWQgYXM6CgpzdHJ1Y3Qgc3BpbmFuZF9vcF90ZW1wbGF0ZXMgewog CXN0cnVjdCBzcGlfbWVtX29wIHJlYWRfY2FjaGU7CiAJc3RydWN0IHNwaV9tZW1fb3Agd3JpdGVf Y2FjaGU7CiAJc3RydWN0IHNwaV9tZW1fb3AgdXBkYXRlX2NhY2hlOwogCXN0cnVjdCBzcGlfbWVt X29wIHJlc2V0OwogCXN0cnVjdCBzcGlfbWVtX29wIGdldF9mZWF0dXJlOwogCXN0cnVjdCBzcGlf bWVtX29wIHNldF9mZWF0dXJlOwogCXN0cnVjdCBzcGlfbWVtX29wIHdyaXRlX2VuYWJsZTsKIAlz dHJ1Y3Qgc3BpX21lbV9vcCBibG9ja19lcmFzZTsKIAlzdHJ1Y3Qgc3BpX21lbV9vcCBwYWdlX2xv YWQ7CiAJc3RydWN0IHNwaV9tZW1fb3AgcHJvZ3JhbV9leGVjdXRlOwp9OwoKc28gdGhlIE5BTkQg ZnJhbWV3b3JrIGNhbiBwb3B1bGF0ZSB0aGVzZSBvcHMuCgpPciBtYXliZSBldmVuIGJldHRlciwg ZGVmaW5lIGFuIGVudW0gdGhhdCBjb250YWlucyBhbGwgdGhlIG9wczoKCmVudW0gc3BpbmFuZF9v cF9pZCB7CglTUElfTkFORF9PUF9SRUFEX0NBQ0hFLAoJU1BJX05BTkRfT1BfV1JJVEVfQ0FDSEUs CglTUElfTkFORF9PUF9VUERBVEVfQ0FDSEUsCglTUElfTkFORF9PUF9SRVNFVCwKLi4uCglTUElf TkFORF9OVU1fT1BTLAp9OwoKc3RydWN0IHNwaW5hbmRfZGV2aWNlIHsKCS4uLgogCWVudW0gc3Bp bmFuZF9wcm90b2NvbCBwcm90b2NvbDsKIAlzdHJ1Y3Qgc3BpX21lbV9vcCBvcF90ZW1wbGF0ZXNb U1BJTkFORF9OVU1fUFJPVE9DT0xTXVtTUElfTkFORF9OVU1fT1BTXTsKCS4uLgp9OwoKPiA+Cj4g PiBUaGlzIHdheSwgeW91IGNhbiBlYXNpbHkgcGljayB0aGUgcmlnaHQgc2V0IG9mIG9wZXJhdGlv bnMgYmFzZWQKPiA+IG9uIHRoZSBwcm90b2NvbC9tb2RlIHlvdSdyZSBpbjoKPiA+Cj4gPiAjZGVm aW5lIHNwaW5hbmRfZ2V0X29wX3RlbXBsYXRlKHNwaW5hbmQsIG9wbmFtZSkgXAo+ID4gCSgoc3Bp bmFuZCktPm9wX3RlbXBsYXRlc1soc3BpbmFuZCktPnByb3RvY29sXS0+b3BuYW1lKQo+ID4KPiA+ IHN0YXRpYyBpbnQgc3BpbmFuZF9yZWFkX3JlZ19vcChzdHJ1Y3Qgc3BpbmFuZF9kZXZpY2UgKnNw aW5hbmQsIHU4IHJlZywgdTggKnZhbCkKPiA+IHsKPiA+IAlzdHJ1Y3Qgc3BpX21lbV9vcCBvcCA9 ICpzcGluYW5kX2dldF9vcF90ZW1wbGF0ZShzcGluYW5kLCBnZXRfZmVhdHVyZSk7Cj4gPiAJaW50 IHJldDsKPiA+Cj4gPiAJLi4uCj4gPiB9ICAKPiAKPiBJIGZpbmQgYSBjb3VwbGUgb2YgaXNzdWVz IHdpdGggdGhpc8KgIG1ldGhvZCwKPiAKPiAxLiByZWFkX2NhY2hlLCB3cml0ZV9jYWNoZSwgdXBk YXRlX2NhY2hlIG9wIHRlbXBsYXRlcyBkb24ndCBmaXQgd2VsbCAKPiB3aXRoIHRoZSBvdGhlciBu b24tZGF0YSBvcHMsIGFzCj4gdGhlc2UgZGF0YSBvcHMgYXJlIHVzZWQgdG8gY3JlYXRlIGEgZGly bWFwLCBhbmQgdGhhdCBjYW4gYmUgZG9uZSBvbmx5IAo+IG9uY2UgYXQgcHJvYmUgdGltZS4gSGVu Y2UsIHRoZXJlCj4gaXMgYSBkaWZmZXJlbnQgbWVjaGFuaXNtIG9mIHNlbGVjdGluZyBvZiBkYXRh IG9wcyBhbmQgbm9uLWRhdGEgb3BzLiAKCk5vdCBzdXJlIEkgc2VlIHdoeSB0aGlzIGlzIGEgcHJv YmxlbS4gWW91IGNhbiBwb3B1bGF0ZSBkYXRhLW9wcyBmb3IgYWxsCm1vZGVzLCBhbmQgcGljayB0 aGUgb25lIHRoYXQgcHJvdmlkZXMgdGhlIGJlc3QgcGVyZnMgd2hlbiB5b3UgY3JlYXRlCnRoZSBk aXJtYXAgKHdoaWNoIHNob3VsZCByZWFsbHkgYmUgYXQgdGhlIGVuZCBvZiB0aGUgcHJvYmUsIGlm IGl0J3Mgbm90CmFscmVhZHkpLgoKPiBIZW5jZSwgdGhpcyBkaXZpc2lvbiBpbiB0aGUgb3AgdGVt cGxhdGVzCj4gc3RydWN0IGFzIGRhdGFfb3BzIGFuZCBjdHJsX29wcyBpcyByZXF1aXJlZC4gQ3Vy cmVudGx5LCB0aGUgY29yZSBvbmx5IAo+IHN1cHBvcnRzIHVzaW5nIGEgc2luZ2xlIHByb3RvY29s IGZvcgo+IGRhdGEgb3BzLCBjaG9zZW4gYXQgdGhlIHRpbWUgb2YgcHJvYmluZy4KCkFnYWluLCBJ IGRvbid0IHNlZSB3aHkgeW91IG5lZWQgdG8gZGlmZmVyZW50aWF0ZSB0aGUgY29udHJvbCBhbmQg ZGF0YQpvcHMgd2hlbiBwb3B1bGF0aW5nIHRoaXMgdGFibGUuIFRob3NlIGFyZSBqdXN0IG9wZXJh dGlvbnMgdGhlIE5BTkQKc3VwcG9ydHMsIGFuZCB0aGUgZGF0YSBvcGVyYXRpb25zIGlzIGp1c3Qg YSBzdWJzZXQuCgo+IAo+IDIuIElmIHdlIHVzZSB0aGlzIHNpbmdsZSBvcF90ZW1wbGF0ZXMgc3Ry dWN0LCBJIGNhbid0IHRoaW5rIG9mIGFueSBnb29kIAo+IHdheSB0byBpbml0aWFsaXplIHRoZXNl IGluIHRoZQo+IG1hbnVmYWN0dXJlcnMgZHJpdmVyICh3aW5ib25kLmMpLCByZWZlciB0byAxN3Ro IHBhdGNoIGluIHRoaXMgc2VyaWVzLiAKPiBDb3VsZCB5b3UgcGxlYXNlIHN1Z2dlc3QgYSBtYWNy bwo+IGltcGxlbWVudGF0aW9uIGFsc28gZm9yIHdpbmJvbmQuYyB3aXRoIHRoZSBzdWdnZXN0ZWQg b3BfdGVtcGxhdGVzIHN0cnVjdC4KCkZpcnN0IHJlcGxhY2UgdGhlIG9wX3ZhcmlhbnRzIGZpZWxk IGJ5IHNvbWV0aGluZyBtb3JlIGdlbmVyaWM6CgpzdHJ1Y3Qgc3BpbmFuZF9pbmZvIHsKLi4uCglj b25zdCBzdHJ1Y3Qgc3BpbmFuZF9vcF92YXJpYW50cyAqKm9wc192YXJpYW50czsKLi4uCn07Cgoj ZGVmaW5lIFNQSU5BTkRfT1BfVkFSSUFOVFMoX2lkLCAuLi4pIFwKCVtTUElfTkFORF9PUF8gIyMg X2lkXSA9IHsgX19WQV9BUkdTX18gfQoKI2RlZmluZSBTUElOQU5EX09QU19WQVJJQU5UUyhuYW1l LCAuLi4pCgljb25zdCBzdHJ1Y3Qgc3BpbmFuZF9vcF92YXJpYW50cyBuYW1lW117CgkJX19WQV9B UkdTX18sCgl9OwoKI2RlZmluZSBTUElOQU5EX0lORk9fT1BTX1ZBUklBTlRTKGRlZnMpCgkub3Bz X3ZhcmlhbnRzID0gZGVmcwoKLi4uCgpzdGF0aWMgU1BJTkFORF9PUFNfVkFSSUFOVFModzM1bjAx andfb3BzX3ZhcmlhbnRzLAoJCVNQSU5BTkRfT1BfVkFSSUFOVFMoUkVBRF9DQUNIRSwKCQkJU1BJ TkFORF9QQUdFX1JFQURfRlJPTV9DQUNIRV9PQ1RBTElPX0RUUl9PUCgwLCAyNCwgTlVMTCwgMCks CgkJCVNQSU5BTkRfUEFHRV9SRUFEX0ZST01fQ0FDSEVfT1AodHJ1ZSwgMCwgMSwgTlVMTCwgMCks CgkJCS4uLikpLAoJCVNQSU5BTkRfT1BfVkFSSUFOVFMoV1JJVEVfQ0FDSEUsCgkJCVNQSU5BTkRf UFJPR19MT0FEX09DVEFMSU9fRFRSKHRydWUsIDAsIE5VTEwsIDApLAoJCQlTUElOQU5EX1BST0df TE9BRCh0cnVlLCAwLCBOVUxMLCAwKSksCgkJLi4uCgkJU1BJTkFORF9PUF9WQVJJQU5UUyhSRVNF VCwKCQkJU1BJTkFORF9SRVNFVF9PUF9PQ1RBTF9EVFIsCgkJCVNQSU5BTkRfUkVTRVRfT1AsCgkJ Li4uCgkJKTsKLi4uCgoKCVNQSU5BTkRfSU5GTygiVzM1TjAxSlciLAoJCSAgICAgU1BJTkFORF9J RChTUElOQU5EX1JFQURJRF9NRVRIT0RfT1BDT0RFX0RVTU1ZLCAweGRjKSwKCQkgICAgIE5BTkRf TUVNT1JHKDEsIDQwOTYsIDEyOCwgNjQsIDUxMiwgMjAsIDEsIDEsIDEpLAoJCSAgICAgTkFORF9F Q0NSRVEoMSwgNTEyKSwKCQkgICAgIFNQSU5BTkRfSEFTX09DVEFMX0RUUl9CSVQgfCBTUElOQU5E X0hBU19DUl9GRUFUX0JJVCwKCQkgICAgIFNQSU5BTkRfRUNDSU5GTygmdzM1bjAxandfb29ibGF5 b3V0LCBOVUxMKSwKCQkgICAgIFNQSU5BTkRfSU5GT19PUFNfVkFSSUFOVFMoJnczNW4wMWp3X29w c192YXJpYW50cykpLAoKWW91IGFsc28gbmVlZCB0byBhZGp1c3Qgc3BpbmFuZF9tYXRjaF9hbmRf aW5pdCgpIHRvIGFjY291bnQgZm9yIHRoaXMKbmV3IGxheW91dCBhbmQgcHV0IGVhY2ggdGVtcGxh dGUgb3AgaW4gdGhlIHJpZ2h0IHN1YnNldCBiYXNlZCBvbgpvcC5jbWQud2lkdGggYW5kIG9wLmNt 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18:37:05 +0100 From: Boris Brezillon To: Apurva Nandan Cc: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Patrice Chotard , Christophe Kerello , Daniel Palmer , Alexander Lobakin , , , , Subject: Re: [PATCH v3 05/17] mtd: spinand: Define ctrl_ops for non-page read/write op templates Message-ID: <20220215183705.574df0c1@collabora.com> In-Reply-To: References: <20220101074250.14443-1-a-nandan@ti.com> <20220101074250.14443-6-a-nandan@ti.com> <20220103110107.45594e78@collabora.com> Organization: Collabora X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.31; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Hi Apurva, On Tue, 15 Feb 2022 21:03:52 +0530 Apurva Nandan wrote: > Hi Boris, >=20 > On 03/01/22 15:31, Boris Brezillon wrote: > > On Sat, 1 Jan 2022 13:12:38 +0530 > > Apurva Nandan wrote: > > =20 > >> 'ctrl_ops' are op templates for non-page read/write operations, > >> which are: reset, get_feature, set_feature, write_enable, block_erase, > >> page_read and program_execute ops. The 'ctrl_ops' struct contains in it > >> op templates for each of this op, as well as enum spinand_protocol > >> denoting protocol of all these ops. > >> > >> We require these new op templates because of deviation in standard > >> SPINAND ops by manufacturers and also due to changes when there is a > >> change in SPI protocol/mode. This prevents the core from live-patching > >> and vendor-specific adjustments in ops. > >> > >> Define 'ctrl_ops', add macros to initialize it and add it in > >> spinand_device. > >> > >> Signed-off-by: Apurva Nandan > >> --- > >> include/linux/mtd/spinand.h | 33 +++++++++++++++++++++++++++++++++ > >> 1 file changed, 33 insertions(+) > >> > >> diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h > >> index 439d8ce40e1d..e5df6220ec1e 100644 > >> --- a/include/linux/mtd/spinand.h > >> +++ b/include/linux/mtd/spinand.h > >> @@ -356,6 +356,35 @@ struct spinand_op_variants { > >> sizeof(struct spi_mem_op), \ > >> } > >> =20 > >> +struct spinand_ctrl_ops { > >> + const struct { > >> + struct spi_mem_op reset; > >> + struct spi_mem_op get_feature; > >> + struct spi_mem_op set_feature; > >> + struct spi_mem_op write_enable; > >> + struct spi_mem_op block_erase; > >> + struct spi_mem_op page_read; > >> + struct spi_mem_op program_execute; > >> + } ops; > >> + const enum spinand_protocol protocol; =20 > > Do you really need that protocol field? > > =20 > >> +}; > >> + > >> +#define SPINAND_CTRL_OPS(__protocol, __reset, __get_feature, __set_fe= ature, \ > >> + __write_enable, __block_erase, __page_read, \ > >> + __program_execute) \ > >> + { \ > >> + .ops =3D { \ > >> + .reset =3D __reset, \ > >> + .get_feature =3D __get_feature, \ > >> + .set_feature =3D __set_feature, \ > >> + .write_enable =3D __write_enable, \ > >> + .block_erase =3D __block_erase, \ > >> + .page_read =3D __page_read, \ > >> + .program_execute =3D __program_execute, \ > >> + }, \ > >> + .protocol =3D __protocol, \ > >> + } > >> + > >> /** > >> * spinand_ecc_info - description of the on-die ECC implemented by a= SPI NAND > >> * chip > >> @@ -468,6 +497,8 @@ struct spinand_dirmap { > >> * @data_ops.read_cache: read cache op template > >> * @data_ops.write_cache: write cache op template > >> * @data_ops.update_cache: update cache op template > >> + * @ctrl_ops: various SPI mem op templates for handling the flash dev= ice, i.e. > >> + * non page-read/write ops. > >> * @select_target: select a specific target/die. Usually called befo= re sending > >> * a command addressing a page or an eraseblock embedded in > >> * this die. Only required if your chip exposes several dies > >> @@ -498,6 +529,8 @@ struct spinand_device { > >> const struct spi_mem_op *update_cache; > >> } data_ops; > >> =20 > >> + const struct spinand_ctrl_ops *ctrl_ops; > >> + =20 > > Okay, I had something slightly different in mind. First, I'd put all > > templates in a struct: > > > > struct spinand_op_templates { > > const struct spi_mem_op *read_cache; > > const struct spi_mem_op *write_cache; > > const struct spi_mem_op *update_cache; > > const struct spi_mem_op *reset; > > const struct spi_mem_op *get_feature; > > const struct spi_mem_op *set_feature; > > const struct spi_mem_op *write_enable; > > const struct spi_mem_op *block_erase; > > const struct spi_mem_op *page_load; > > const struct spi_mem_op *program_execute; > > }; > > > > Then, at the spinand level, I'd define an array of templates: > > > > enum spinand_protocol { > > SPINAND_1S_1S_1S, > > SPINAND_2S_2S_2S, > > SPINAND_4S_4S_4S, > > SPINAND_8S_8S_8S, > > SPINAND_8D_8D_8D, > > SPINAND_NUM_PROTOCOLS, > > }; > > > > struct spinand_device { > > ... > > enum spinand_protocol protocol; > > const struct spinand_op_templates *op_templates[SPINAND_NUM_PROTOCOLS]; It should probably be struct spinand_op_templates op_templates[SPINAND_NUM_PROTOCOLS]; with the spinand_op_templates struct defined as: struct spinand_op_templates { struct spi_mem_op read_cache; struct spi_mem_op write_cache; struct spi_mem_op update_cache; struct spi_mem_op reset; struct spi_mem_op get_feature; struct spi_mem_op set_feature; struct spi_mem_op write_enable; struct spi_mem_op block_erase; struct spi_mem_op page_load; struct spi_mem_op program_execute; }; so the NAND framework can populate these ops. Or maybe even better, define an enum that contains all the ops: enum spinand_op_id { SPI_NAND_OP_READ_CACHE, SPI_NAND_OP_WRITE_CACHE, SPI_NAND_OP_UPDATE_CACHE, SPI_NAND_OP_RESET, ... SPI_NAND_NUM_OPS, }; struct spinand_device { ... enum spinand_protocol protocol; struct spi_mem_op op_templates[SPINAND_NUM_PROTOCOLS][SPI_NAND_NUM_OPS]; ... }; > > > > This way, you can easily pick the right set of operations based > > on the protocol/mode you're in: > > > > #define spinand_get_op_template(spinand, opname) \ > > ((spinand)->op_templates[(spinand)->protocol]->opname) > > > > static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, = u8 *val) > > { > > struct spi_mem_op op =3D *spinand_get_op_template(spinand, get_feature= ); > > int ret; > > > > ... > > } =20 >=20 > I find a couple of issues with this=C2=A0 method, >=20 > 1. read_cache, write_cache, update_cache op templates don't fit well=20 > with the other non-data ops, as > these data ops are used to create a dirmap, and that can be done only=20 > once at probe time. Hence, there > is a different mechanism of selecting of data ops and non-data ops.=20 Not sure I see why this is a problem. You can populate data-ops for all modes, and pick the one that provides the best perfs when you create the dirmap (which should really be at the end of the probe, if it's not already). > Hence, this division in the op templates > struct as data_ops and ctrl_ops is required. Currently, the core only=20 > supports using a single protocol for > data ops, chosen at the time of probing. Again, I don't see why you need to differentiate the control and data ops when populating this table. Those are just operations the NAND supports, and the data operations is just a subset. >=20 > 2. If we use this single op_templates struct, I can't think of any good=20 > way to initialize these in the > manufacturers driver (winbond.c), refer to 17th patch in this series.=20 > Could you please suggest a macro > implementation also for winbond.c with the suggested op_templates struct. First replace the op_variants field by something more generic: struct spinand_info { ... const struct spinand_op_variants **ops_variants; ... }; #define SPINAND_OP_VARIANTS(_id, ...) \ [SPI_NAND_OP_ ## _id] =3D { __VA_ARGS__ } #define SPINAND_OPS_VARIANTS(name, ...) const struct spinand_op_variants name[]{ __VA_ARGS__, }; #define SPINAND_INFO_OPS_VARIANTS(defs) .ops_variants =3D defs ... static SPINAND_OPS_VARIANTS(w35n01jw_ops_variants, SPINAND_OP_VARIANTS(READ_CACHE, SPINAND_PAGE_READ_FROM_CACHE_OCTALIO_DTR_OP(0, 24, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), ...)), SPINAND_OP_VARIANTS(WRITE_CACHE, SPINAND_PROG_LOAD_OCTALIO_DTR(true, 0, NULL, 0), SPINAND_PROG_LOAD(true, 0, NULL, 0)), ... SPINAND_OP_VARIANTS(RESET, SPINAND_RESET_OP_OCTAL_DTR, SPINAND_RESET_OP, ... ); ... SPINAND_INFO("W35N01JW", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdc), NAND_MEMORG(1, 4096, 128, 64, 512, 20, 1, 1, 1), NAND_ECCREQ(1, 512), SPINAND_HAS_OCTAL_DTR_BIT | SPINAND_HAS_CR_FEAT_BIT, SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL), SPINAND_INFO_OPS_VARIANTS(&w35n01jw_ops_variants)), You also need to adjust spinand_match_and_init() to account for this new layout and put each template op in the right subset based on op.cmd.width and op.cmd.dtr. Regards, Boris