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From: kernel test robot <lkp@intel.com>
To: Atish Patra <atishp@rivosinc.com>
Cc: llvm@lists.linux.dev, kbuild-all@lists.01.org
Subject: Re: [PATCH v5 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions
Date: Wed, 23 Feb 2022 09:13:20 +0800	[thread overview]
Message-ID: <202202230903.M0qWlyy9-lkp@intel.com> (raw)
In-Reply-To: <20220222204811.2281949-7-atishp@rivosinc.com>

Hi Atish,

I love your patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on v5.17-rc5 next-20220217]
[cannot apply to linux/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Atish-Patra/Provide-a-fraemework-for-RISC-V-ISA-extensions/20220223-045009
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 917bbdb107f8767cb78f24e7d6725a2f93b9effe
config: riscv-randconfig-r042-20220221 (https://download.01.org/0day-ci/archive/20220223/202202230903.M0qWlyy9-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project d271fc04d5b97b12e6b797c6067d3c96a8d7470e)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install riscv cross compiling tool for clang build
        # apt-get install binutils-riscv64-linux-gnu
        # https://github.com/0day-ci/linux/commit/a37fdf595f84ec4073cb280703a36d440a7e8f96
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Atish-Patra/Provide-a-fraemework-for-RISC-V-ISA-extensions/20220223-045009
        git checkout a37fdf595f84ec4073cb280703a36d440a7e8f96
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash arch/riscv/kernel/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> arch/riscv/kernel/cpu.c:99: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
    * These are the only valid base (single letter) ISA extensions as per the spec.


vim +99 arch/riscv/kernel/cpu.c

    97	
    98	/**
  > 99	 * These are the only valid base (single letter) ISA extensions as per the spec.
   100	 * It also specifies the canonical order in which it appears in the spec.
   101	 * Some of the extension may just be a place holder for now (B, K, P, J).
   102	 * This should be updated once corresponding extensions are ratified.
   103	 */
   104	static const char base_riscv_exts[13] = "imafdqcbkjpvh";
   105	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

  reply	other threads:[~2022-02-23  1:14 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-22 20:48 [PATCH v5 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra
2022-02-22 20:48 ` Atish Patra
2022-02-22 20:48 ` [PATCH v5 1/6] RISC-V: Correctly print supported extensions Atish Patra
2022-02-22 20:48   ` Atish Patra
2022-02-22 20:48 ` [PATCH v5 2/6] RISC-V: Minimal parser for "riscv, isa" strings Atish Patra
2022-02-22 20:48   ` Atish Patra
2022-02-28 10:03   ` Anup Patel
2022-02-28 10:03     ` Anup Patel
2022-02-22 20:48 ` [PATCH v5 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa" Atish Patra
2022-02-22 20:48   ` Atish Patra
2022-02-28 10:03   ` Anup Patel
2022-02-28 10:03     ` Anup Patel
2022-02-22 20:48 ` [PATCH v5 4/6] RISC-V: Implement multi-letter ISA extension probing framework Atish Patra
2022-02-22 20:48   ` Atish Patra
2022-02-28 10:06   ` Anup Patel
2022-02-28 10:06     ` Anup Patel
2022-02-22 20:48 ` [PATCH v5 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Atish Patra
2022-02-22 20:48   ` Atish Patra
2022-02-28 10:06   ` Anup Patel
2022-02-28 10:06     ` Anup Patel
2022-02-22 20:48 ` [PATCH v5 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Atish Patra
2022-02-22 20:48   ` Atish Patra
2022-02-23  1:13   ` kernel test robot [this message]
2022-02-28 10:07   ` Anup Patel
2022-02-28 10:07     ` Anup Patel
2022-03-10 23:50 ` [PATCH v5 0/6] Provide a fraemework for RISC-V " Palmer Dabbelt
2022-03-10 23:50   ` Palmer Dabbelt
2022-03-11  0:21   ` Atish Kumar Patra
2022-03-11  0:21     ` Atish Kumar Patra
2022-03-11 12:42     ` Nick Kossifidis
2022-03-11 12:42       ` Nick Kossifidis
2022-03-11 13:10       ` Anup Patel
2022-03-11 13:10         ` Anup Patel

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