From: Segher Boessenkool <segher@kernel.crashing.org>
To: Gabriel Paubert <paubert@iram.es>
Cc: linuxppc-dev@lists.ozlabs.org, Paul Mackerras <paulus@samba.org>,
Kees Cook <keescook@chromium.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] powerpc/32: Clear volatile regs on syscall exit
Date: Wed, 23 Feb 2022 17:27:39 -0600 [thread overview]
Message-ID: <20220223232739.GJ614@gate.crashing.org> (raw)
In-Reply-To: <YhadiVbwao/p2N7o@lt-gp.iram.es>
On Wed, Feb 23, 2022 at 09:48:09PM +0100, Gabriel Paubert wrote:
> On Wed, Feb 23, 2022 at 06:11:36PM +0100, Christophe Leroy wrote:
> > + /* Zero volatile regs that may contain sensitive kernel data */
> > + li r0,0
> > + li r4,0
> > + li r5,0
> > + li r6,0
> > + li r7,0
> > + li r8,0
> > + li r9,0
> > + li r10,0
> > + li r11,0
> > + li r12,0
> > + mtctr r0
> > + mtxer r0
>
> Here, I'm almost sure that on some processors, it would be better to
> separate mtctr form mtxer. mtxer is typically very expensive (pipeline
> flush) but I don't know what's the best ordering for the average core.
mtxer is cheaper than mtctr on many cores :-)
On p9 mtxer is cracked into two latency 3 ops (which run in parallel).
While mtctr has latency 5.
On p8 mtxer was horrible indeed (but nothing near as bad as a pipeline
flush).
Segher
WARNING: multiple messages have this Message-ID (diff)
From: Segher Boessenkool <segher@kernel.crashing.org>
To: Gabriel Paubert <paubert@iram.es>
Cc: Christophe Leroy <christophe.leroy@csgroup.eu>,
Kees Cook <keescook@chromium.org>,
linux-kernel@vger.kernel.org, Paul Mackerras <paulus@samba.org>,
linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH] powerpc/32: Clear volatile regs on syscall exit
Date: Wed, 23 Feb 2022 17:27:39 -0600 [thread overview]
Message-ID: <20220223232739.GJ614@gate.crashing.org> (raw)
In-Reply-To: <YhadiVbwao/p2N7o@lt-gp.iram.es>
On Wed, Feb 23, 2022 at 09:48:09PM +0100, Gabriel Paubert wrote:
> On Wed, Feb 23, 2022 at 06:11:36PM +0100, Christophe Leroy wrote:
> > + /* Zero volatile regs that may contain sensitive kernel data */
> > + li r0,0
> > + li r4,0
> > + li r5,0
> > + li r6,0
> > + li r7,0
> > + li r8,0
> > + li r9,0
> > + li r10,0
> > + li r11,0
> > + li r12,0
> > + mtctr r0
> > + mtxer r0
>
> Here, I'm almost sure that on some processors, it would be better to
> separate mtctr form mtxer. mtxer is typically very expensive (pipeline
> flush) but I don't know what's the best ordering for the average core.
mtxer is cheaper than mtctr on many cores :-)
On p9 mtxer is cracked into two latency 3 ops (which run in parallel).
While mtctr has latency 5.
On p8 mtxer was horrible indeed (but nothing near as bad as a pipeline
flush).
Segher
next prev parent reply other threads:[~2022-02-24 9:10 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-23 17:11 [PATCH] powerpc/32: Clear volatile regs on syscall exit Christophe Leroy
2022-02-23 17:11 ` Christophe Leroy
2022-02-23 19:34 ` Kees Cook
2022-02-23 19:34 ` Kees Cook
2022-02-24 7:00 ` Christophe Leroy
2022-02-24 7:00 ` Christophe Leroy
2022-02-23 20:48 ` Gabriel Paubert
2022-02-23 20:48 ` Gabriel Paubert
2022-02-23 23:27 ` Segher Boessenkool [this message]
2022-02-23 23:27 ` Segher Boessenkool
2022-02-24 8:29 ` Gabriel Paubert
2022-02-24 8:29 ` Gabriel Paubert
2022-02-24 12:49 ` Segher Boessenkool
2022-02-24 12:49 ` Segher Boessenkool
2022-02-24 6:41 ` Christophe Leroy
2022-02-24 6:41 ` Christophe Leroy
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