From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7AFDBC433EF for ; Thu, 24 Feb 2022 13:42:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:CC:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JaH2Q7VEq1x4DPdKbNplelI27Cf7yyReBrhuE56+JwI=; b=3EGP4HplNMxbfI av04ga7A/uLXIBBRBcghhnRq23RGyPtkGeUTwD/aYkX9RY2ignyD5ku9zOdB2PhcUUtURRSEEc5R5 IqaF+NT3dI1bwHMAgLgglm/IfejWJGG29+Q9G7pgK/b50hxylce9Z+pcnhJ2LLuzlztnxLgu7noeo TFlFWpJdDqD1ipTOYZUy3WTFd7A/XVcEC+tRctNiEqVKfo6AeWBlLgcPUDAXCPfJTzsUX4uFGRCCj Op3B7A6/cFViXyYPg26cuEn+g8q4CgiOuT/Ap9BxyuRMrcPmfpHmrI5K6B0C2woovfGwKI5w9IXvW JX4BfCj/k7qijlL/+1Kg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nNEMr-000yW3-Oc; Thu, 24 Feb 2022 13:41:13 +0000 Received: from smtp2.axis.com ([195.60.68.18]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nNEMg-000yRs-JA for linux-arm-kernel@lists.infradead.org; Thu, 24 Feb 2022 13:41:10 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1645710063; x=1677246063; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=yj/Kubo401FMKbYI1pppYqnrVxPghG1puNDBjNlL3v4=; b=fdINDqN/2s5R0OehvsPEkWZvmAjBZxEjsQZkI0djW+hM2dY6bkBqosMg hJWbpnaJ+JLkttIiGV6dEiM33WeLDOBIp0YC1i0Hm/qmXXzLLrmiC7AUs k58tj0A/JY7Ecpy5nc5POCzDwqeLJuKK/FTEnjM3YENU8jKFT3r6c9El5 NeE2yQSYvcu+O0BloaX72jBckRT57XVHoBkBr7KSMmMmmOM3DD9Q8b/uu sZffmirMoJYzUAY84W4449SzDr8J0tnHgrywNLtIUwm56MQCbSAXlL9SN JTePICoPW/zNrA/Qj3YyXiv0NXPxP+KzmoTovsMw2M9nvHOdR2LXt9NiS g==; Date: Thu, 24 Feb 2022 14:40:57 +0100 From: Vincent Whitchurch To: Denis Kirjanov CC: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Jakub Kicinski , Maxime Coquelin , kernel , Lars Persson , Srinivas Kandagatla , "netdev@vger.kernel.org" , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v2] net: stmmac: only enable DMA interrupts when ready Message-ID: <20220224134057.GA4994@axis.com> References: <20220224113829.1092859-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220224_054103_938877_EFF98D78 X-CRM114-Status: GOOD ( 14.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gVGh1LCBGZWIgMjQsIDIwMjIgYXQgMDE6NTM6MzNQTSArMDEwMCwgRGVuaXMgS2lyamFub3Yg d3JvdGU6Cj4gMi8yNC8yMiAxNDozOCwgVmluY2VudCBXaGl0Y2h1cmNoINC/0LjRiNC10YI6Cj4g PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9uZXQvZXRoZXJuZXQvc3RtaWNyby9zdG1tYWMvc3RtbWFj X21haW4uYyBiL2RyaXZlcnMvbmV0L2V0aGVybmV0L3N0bWljcm8vc3RtbWFjL3N0bW1hY19tYWlu LmMKPiA+IGluZGV4IDY3MDhjYTJhYTRmNy4uNDM5Nzg1NThkNmMwIDEwMDY0NAo+ID4gLS0tIGEv ZHJpdmVycy9uZXQvZXRoZXJuZXQvc3RtaWNyby9zdG1tYWMvc3RtbWFjX21haW4uYwo+ID4gKysr IGIvZHJpdmVycy9uZXQvZXRoZXJuZXQvc3RtaWNyby9zdG1tYWMvc3RtbWFjX21haW4uYwo+ID4g QEAgLTIyNjAsNiArMjI2MCwyMyBAQCBzdGF0aWMgdm9pZCBzdG1tYWNfc3RvcF90eF9kbWEoc3Ry dWN0IHN0bW1hY19wcml2ICpwcml2LCB1MzIgY2hhbikKPiA+ICAgCXN0bW1hY19zdG9wX3R4KHBy aXYsIHByaXYtPmlvYWRkciwgY2hhbik7Cj4gPiAgIH0KPiA+ICAgCj4gPiArc3RhdGljIHZvaWQg c3RtbWFjX2VuYWJsZV9hbGxfZG1hX2lycShzdHJ1Y3Qgc3RtbWFjX3ByaXYgKnByaXYpCj4gPiAr ewo+ID4gKwl1MzIgcnhfY2hhbm5lbHNfY291bnQgPSBwcml2LT5wbGF0LT5yeF9xdWV1ZXNfdG9f dXNlOwo+ID4gKwl1MzIgdHhfY2hhbm5lbHNfY291bnQgPSBwcml2LT5wbGF0LT50eF9xdWV1ZXNf dG9fdXNlOwo+ID4gKwl1MzIgZG1hX2Nzcl9jaCA9IG1heChyeF9jaGFubmVsc19jb3VudCwgdHhf Y2hhbm5lbHNfY291bnQpOwo+ID4gKwl1MzIgY2hhbjsKPiA+ICsKPiA+ICsJZm9yIChjaGFuID0g MDsgY2hhbiA8IGRtYV9jc3JfY2g7IGNoYW4rKykgewo+ID4gKwkJc3RydWN0IHN0bW1hY19jaGFu bmVsICpjaCA9ICZwcml2LT5jaGFubmVsW2NoYW5dOwo+ID4gKwkJdW5zaWduZWQgbG9uZyBmbGFn czsKPiA+ICsKPiA+ICsJCXNwaW5fbG9ja19pcnFzYXZlKCZjaC0+bG9jaywgZmxhZ3MpOwo+ID4g KwkJc3RtbWFjX2VuYWJsZV9kbWFfaXJxKHByaXYsIHByaXYtPmlvYWRkciwgY2hhbiwgMSwgMSk7 Cj4gPiArCQlzcGluX3VubG9ja19pcnFyZXN0b3JlKCZjaC0+bG9jaywgZmxhZ3MpOwo+ID4gKwl9 Cj4gPiArfQo+ID4gKwo+ID4gICAvKioKPiA+ICAgICogc3RtbWFjX3N0YXJ0X2FsbF9kbWEgLSBz dGFydCBhbGwgUlggYW5kIFRYIERNQSBjaGFubmVscwo+ID4gICAgKiBAcHJpdjogZHJpdmVyIHBy aXZhdGUgc3RydWN0dXJlCj4gPiBAQCAtMjkwMiw4ICsyOTE5LDEwIEBAIHN0YXRpYyBpbnQgc3Rt bWFjX2luaXRfZG1hX2VuZ2luZShzdHJ1Y3Qgc3RtbWFjX3ByaXYgKnByaXYpCj4gPiAgIAkJc3Rt bWFjX2F4aShwcml2LCBwcml2LT5pb2FkZHIsIHByaXYtPnBsYXQtPmF4aSk7Cj4gPiAgIAo+ID4g ICAJLyogRE1BIENTUiBDaGFubmVsIGNvbmZpZ3VyYXRpb24gKi8KPiA+IC0JZm9yIChjaGFuID0g MDsgY2hhbiA8IGRtYV9jc3JfY2g7IGNoYW4rKykKPiA+ICsJZm9yIChjaGFuID0gMDsgY2hhbiA8 IGRtYV9jc3JfY2g7IGNoYW4rKykgewo+ID4gICAJCXN0bW1hY19pbml0X2NoYW4ocHJpdiwgcHJp di0+aW9hZGRyLCBwcml2LT5wbGF0LT5kbWFfY2ZnLCBjaGFuKTsKPiBEaWQgeW91IG1pc3MgdG8g dGFrZSBhIGNoYW5uZWwgbG9jaz8KCkkgZGlkbid0IGFkZCBpdCBvbiBwdXJwb3NlLiAgQXQgdGhp cyBwb2ludCBkdXJpbmcgaW5pdGlhbGl6YXRpb24gdGhlcmUKaXMgbm8tb25lIHdobyBjYW4gcmFj ZSB3aXRoIHRoZSByZWdpc3RlciB3cml0ZSBpbgpzdG1tYWNfZGlzYWJsZV9kbWFfaXJxKCkuICBU aGUgY2FsbCB0byBzdG1tYWNfaW5pdF9jaGFuKCkgKGluIHRoZQpleGlzdGluZyBjb2RlKSB3cml0 ZXMgdGhlIHNhbWUgcmVnaXN0ZXIgd2l0aG91dCB0aGUgbG9jay4gCgo+ID4gKwkJc3RtbWFjX2Rp c2FibGVfZG1hX2lycShwcml2LCBwcml2LT5pb2FkZHIsIGNoYW4sIDEsIDEpOwo+ID4gKwl9Cj4g PiAgIAoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlu dXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRl YWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgt YXJtLWtlcm5lbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B56CC433F5 for ; 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Date: Thu, 24 Feb 2022 14:40:57 +0100 From: Vincent Whitchurch To: Denis Kirjanov CC: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Jakub Kicinski , Maxime Coquelin , kernel , Lars Persson , Srinivas Kandagatla , "netdev@vger.kernel.org" , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v2] net: stmmac: only enable DMA interrupts when ready Message-ID: <20220224134057.GA4994@axis.com> References: <20220224113829.1092859-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Feb 24, 2022 at 01:53:33PM +0100, Denis Kirjanov wrote: > 2/24/22 14:38, Vincent Whitchurch пишет: > > diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c > > index 6708ca2aa4f7..43978558d6c0 100644 > > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c > > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c > > @@ -2260,6 +2260,23 @@ static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) > > stmmac_stop_tx(priv, priv->ioaddr, chan); > > } > > > > +static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv) > > +{ > > + u32 rx_channels_count = priv->plat->rx_queues_to_use; > > + u32 tx_channels_count = priv->plat->tx_queues_to_use; > > + u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); > > + u32 chan; > > + > > + for (chan = 0; chan < dma_csr_ch; chan++) { > > + struct stmmac_channel *ch = &priv->channel[chan]; > > + unsigned long flags; > > + > > + spin_lock_irqsave(&ch->lock, flags); > > + stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); > > + spin_unlock_irqrestore(&ch->lock, flags); > > + } > > +} > > + > > /** > > * stmmac_start_all_dma - start all RX and TX DMA channels > > * @priv: driver private structure > > @@ -2902,8 +2919,10 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv) > > stmmac_axi(priv, priv->ioaddr, priv->plat->axi); > > > > /* DMA CSR Channel configuration */ > > - for (chan = 0; chan < dma_csr_ch; chan++) > > + for (chan = 0; chan < dma_csr_ch; chan++) { > > stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); > Did you miss to take a channel lock? I didn't add it on purpose. At this point during initialization there is no-one who can race with the register write in stmmac_disable_dma_irq(). The call to stmmac_init_chan() (in the existing code) writes the same register without the lock. > > + stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); > > + } > >