From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8325DC433F5 for ; Fri, 25 Feb 2022 09:33:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235025AbiBYJdv (ORCPT ); Fri, 25 Feb 2022 04:33:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236766AbiBYJdv (ORCPT ); Fri, 25 Feb 2022 04:33:51 -0500 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2BAC1C60EC; Fri, 25 Feb 2022 01:33:17 -0800 (PST) Received: by mail-ej1-x62f.google.com with SMTP id p14so9578012ejf.11; Fri, 25 Feb 2022 01:33:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to; bh=wVwXFGjPqrDDJSK8G4NlUrkX3LWHDibAAXwXLRr8zhU=; b=od9VIU2Y+YR/rihaLVf56h6HZXL6oQ2Xaazd0VFgMw8QYGgAtwLyQDY0Muby+Yxlc/ C49i+v7JiTmdK5Zz/kL9SWTClA2ZJ8MMY8DZzSk8XOr6f80uPnA0vXbNB2Y2lLkAHded rU2KFznU7l1zvoIQnWxt/1SzbePyI6aPZJlxfYD2euVRdW9GYTRj48BR1TGktN7w90pf 4Ntnn536n14uLsZPs0o3E2pwZl5z59kEVYEodgg4OCpznB1NOeHiaqJwbwG1JVF3F5oY UUoAJlfvkklglAqHXEE7+cO8lsSSE/2z8p2hEtDh2xruMeWHCFyOOqyWqMOoNwcjapcE VSxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=wVwXFGjPqrDDJSK8G4NlUrkX3LWHDibAAXwXLRr8zhU=; b=HqZl4SnyM0woGznwAYA8HHmmxRZHLpND33hbqvUJis/Cyp6EwlUu6WYku+xaYFhcgf cnwdvBQgMFwXdnTyIE2vAotcgK9/S5hbpWnI7OAXwa5BTALi+OejlvnN/FBVo4QoWgCi PVO+2JB9P7fcb4XPjfFMfI2yzOk8K+KGADuSgidMFeu18MpX6UjvD9ClDVwRj+VZ21OO j/B9BxnqYAvCi3udCjflbJWrK3LQUyu+GMaMvdxSD/BjMwYnyACRP2DSVeKdNLRcVaNY e3ulTK0+6VTJQPXXdUhEUDLrrmmYIjv/4G4j6wf6qsFPv0i0gJc4ISeCz2XUo9yAng19 ZYwA== X-Gm-Message-State: AOAM531F26lNflzIu/V0WaOeLZLN6xkAz5k+WsPTpgxJebotmZlLY26S KvZHQ8cfL3y/QnC963O8fY8= X-Google-Smtp-Source: ABdhPJw6q7dLehrGphqLcggKl5vFOrSHQbhv9gy7yZjIFRQu0S1kAZvDLVs/+c2kVkSb2by7JkxMjQ== X-Received: by 2002:a17:907:75fc:b0:6d5:c6bd:6fbd with SMTP id jz28-20020a17090775fc00b006d5c6bd6fbdmr5383036ejc.695.1645781596237; Fri, 25 Feb 2022 01:33:16 -0800 (PST) Received: from adroid (027-177-184-091.ip-addr.vsenet.de. [91.184.177.27]) by smtp.gmail.com with ESMTPSA id f20-20020a170906739400b006ccc4eb357dsm808195ejl.8.2022.02.25.01.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Feb 2022 01:33:15 -0800 (PST) Date: Fri, 25 Feb 2022 10:33:13 +0100 From: Martin =?iso-8859-1?Q?J=FCcker?= To: Inki Dae Cc: Joonyoung Shim , Seung-Woo Kim , Kyungmin Park , David Airlie , Daniel Vetter , Krzysztof Kozlowski , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Martin =?iso-8859-1?Q?J=FCcker?= Subject: Re: [PATCH] drm/exynos: fimd: add BGR support for exynos4/5 Message-ID: <20220225093313.GA87542@adroid> References: <20220129220153.GA33165@adroid> <5e18705f-79c1-18a7-57f2-74866abe21e9@samsung.com> <20220224232723.GA133007@adroid> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Hello Inki, On Fri, Feb 25, 2022 at 12:52:56PM +0900, Inki Dae wrote: > Hi Martin, > > 22. 2. 25. 08:27에 Martin Jücker 이(가) 쓴 글: > > Hello Inki, > > > > On Thu, Feb 24, 2022 at 10:41:04AM +0900, Inki Dae wrote: > >> Hi Martin. > >> > >> I found that exynos4 and 5 data sheet include documented same register. > >> RGB_ORDER_E field of VIDCONx registers will do same thing. > > > > If I read the manual correctly, this register combined with the > > RGB_ORDER_O makes it possible to map the whole RGB interface output to a > > different order. What my patch provides is a way to configure each > > hardware plane separately while maintaining a consistent output on the > > RGB interface. > > > > Understood. Your patch will allow BGR pixel order per a plane. Seems to be useful because a framebuffer with BGR pixel format can be displayed on screen without any color space conversion. :) > > > Implementing the RGB_ORDER_O and E would need some logic to make sure > > that all planes are always using the same RGB order. > > > >> > >> I'm not sure whether the use of undocumented register is safe or not - maybe some HW bug exists. > > > > I see, that makes sense. Would it be possible then to introduce a new > > compatible, e.g. samsung,exynos4210-fimd-ext which can be used on tested > > Seems providing a new compatible is not a good idea. > > > devices? I know that some other Galaxy Note and S devices with the > > exynos4 chip have the same problem (and solution). > > Could you give me more details about the same problem and its solution on the devices? > It would be useful for us to decide the upstream direction. > > If necessary then we may need to contact HW engineer for clarity. Here is my current understanding of the situation: The issue is related to Android and a recovery image having conflicting pixel formats on the same device. There is a solution in Replicant[1] for this using parameters for the fimd driver to force the pixel format to RGB or BGR. It's using the PNRMODE register on VIDCON0, but this solution needs two separate kernels to be built to add the parameter as the boot loader is not adjustable. This was also discussed in dri-devel irc and it was proposed to expose both formats and fail the atomic commit if userspace tried to use both RGB and BGR formats at the same time. With this approach there should be something on the screen but it might happen that some users can't deal with the failing commits as it's rather difficult to find the cause and fix it on the go. After that I accidentally discovered this undocumented register while reading the old vendor sources and it seems that it fixes all the issues. At least if there are no HW bugs as you mentioned. Kind Regards Martin [1] https://git.replicant.us/replicant-next/kernel_replicant_linux/commit/?h=replicant-11&id=cc5a0615b40cd5ede1eb87a60daa50333701a135 > > Thanks, > Inki Dae > > > > >> > >> Anyway, I'd like to recommend you to use documented register only. > >> > >> Sorry for late and thanks, > >> Inki Dae > > > > Kind Regards > > Martin > > > >> > >> 22. 1. 30. 07:01에 Martin Jücker 이(가) 쓴 글: > >>> In the downstream kernels for exynos4 and exynos5 devices, there is an > >>> undocumented register that controls the order of the RGB output. It can > >>> be set to either normal order or reversed, which enables BGR support for > >>> those SoCs. > >>> > >>> This patch enables the BGR support for all the SoCs that were found to > >>> have at least one device with this logic in the corresponding downstream > >>> kernels. > >>> > >>> Signed-off-by: Martin Jücker > >>> --- > >>> drivers/gpu/drm/exynos/exynos_drm_fimd.c | 42 ++++++++++++++++++++++-- > >>> include/video/samsung_fimd.h | 4 +++ > >>> 2 files changed, 44 insertions(+), 2 deletions(-) > >>> > >>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c > >>> index c735e53939d8..cb632360c968 100644 > >>> --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c > >>> +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c > >>> @@ -109,6 +109,7 @@ struct fimd_driver_data { > >>> unsigned int has_dp_clk:1; > >>> unsigned int has_hw_trigger:1; > >>> unsigned int has_trigger_per_te:1; > >>> + unsigned int has_bgr_support:1; > >>> }; > >>> > >>> static struct fimd_driver_data s3c64xx_fimd_driver_data = { > >>> @@ -138,6 +139,7 @@ static struct fimd_driver_data exynos4_fimd_driver_data = { > >>> .lcdblk_bypass_shift = 1, > >>> .has_shadowcon = 1, > >>> .has_vtsel = 1, > >>> + .has_bgr_support = 1, > >>> }; > >>> > >>> static struct fimd_driver_data exynos5_fimd_driver_data = { > >>> @@ -149,6 +151,7 @@ static struct fimd_driver_data exynos5_fimd_driver_data = { > >>> .has_vidoutcon = 1, > >>> .has_vtsel = 1, > >>> .has_dp_clk = 1, > >>> + .has_bgr_support = 1, > >>> }; > >>> > >>> static struct fimd_driver_data exynos5420_fimd_driver_data = { > >>> @@ -162,6 +165,7 @@ static struct fimd_driver_data exynos5420_fimd_driver_data = { > >>> .has_vtsel = 1, > >>> .has_mic_bypass = 1, > >>> .has_dp_clk = 1, > >>> + .has_bgr_support = 1, > >>> }; > >>> > >>> struct fimd_context { > >>> @@ -226,6 +230,18 @@ static const uint32_t fimd_formats[] = { > >>> DRM_FORMAT_ARGB8888, > >>> }; > >>> > >>> +static const uint32_t fimd_extended_formats[] = { > >>> + DRM_FORMAT_C8, > >>> + DRM_FORMAT_XRGB1555, > >>> + DRM_FORMAT_XBGR1555, > >>> + DRM_FORMAT_RGB565, > >>> + DRM_FORMAT_BGR565, > >>> + DRM_FORMAT_XRGB8888, > >>> + DRM_FORMAT_XBGR8888, > >>> + DRM_FORMAT_ARGB8888, > >>> + DRM_FORMAT_ABGR8888, > >>> +}; > >>> + > >>> static const unsigned int capabilities[WINDOWS_NR] = { > >>> 0, > >>> EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, > >>> @@ -673,21 +689,25 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, > >>> val |= WINCONx_BYTSWP; > >>> break; > >>> case DRM_FORMAT_XRGB1555: > >>> + case DRM_FORMAT_XBGR1555: > >>> val |= WINCON0_BPPMODE_16BPP_1555; > >>> val |= WINCONx_HAWSWP; > >>> val |= WINCONx_BURSTLEN_16WORD; > >>> break; > >>> case DRM_FORMAT_RGB565: > >>> + case DRM_FORMAT_BGR565: > >>> val |= WINCON0_BPPMODE_16BPP_565; > >>> val |= WINCONx_HAWSWP; > >>> val |= WINCONx_BURSTLEN_16WORD; > >>> break; > >>> case DRM_FORMAT_XRGB8888: > >>> + case DRM_FORMAT_XBGR8888: > >>> val |= WINCON0_BPPMODE_24BPP_888; > >>> val |= WINCONx_WSWP; > >>> val |= WINCONx_BURSTLEN_16WORD; > >>> break; > >>> case DRM_FORMAT_ARGB8888: > >>> + case DRM_FORMAT_ABGR8888: > >>> default: > >>> val |= WINCON1_BPPMODE_25BPP_A1888; > >>> val |= WINCONx_WSWP; > >>> @@ -695,6 +715,18 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, > >>> break; > >>> } > >>> > >>> + switch (pixel_format) { > >>> + case DRM_FORMAT_XBGR1555: > >>> + case DRM_FORMAT_XBGR8888: > >>> + case DRM_FORMAT_ABGR8888: > >>> + case DRM_FORMAT_BGR565: > >>> + writel(WIN_RGB_ORDER_REVERSE, ctx->regs + WIN_RGB_ORDER(win)); > >>> + break; > >>> + default: > >>> + writel(WIN_RGB_ORDER_FORWARD, ctx->regs + WIN_RGB_ORDER(win)); > >>> + break; > >>> + } > >>> + > >>> /* > >>> * Setting dma-burst to 16Word causes permanent tearing for very small > >>> * buffers, e.g. cursor buffer. Burst Mode switching which based on > >>> @@ -1074,8 +1106,14 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) > >>> ctx->drm_dev = drm_dev; > >>> > >>> for (i = 0; i < WINDOWS_NR; i++) { > >>> - ctx->configs[i].pixel_formats = fimd_formats; > >>> - ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); > >>> + if (ctx->driver_data->has_bgr_support) { > >>> + ctx->configs[i].pixel_formats = fimd_extended_formats; > >>> + ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_extended_formats); > >>> + } else { > >>> + ctx->configs[i].pixel_formats = fimd_formats; > >>> + ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); > >>> + } > >>> + > >>> ctx->configs[i].zpos = i; > >>> ctx->configs[i].type = fimd_win_types[i]; > >>> ctx->configs[i].capabilities = capabilities[i]; > >>> diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h > >>> index c4a93ce1de48..e6966d187591 100644 > >>> --- a/include/video/samsung_fimd.h > >>> +++ b/include/video/samsung_fimd.h > >>> @@ -476,6 +476,10 @@ > >>> * 1111 -none- -none- -none- -none- -none- > >>> */ > >>> > >>> +#define WIN_RGB_ORDER(_win) (0x2020 + ((_win) * 4)) > >>> +#define WIN_RGB_ORDER_FORWARD (0 << 11) > >>> +#define WIN_RGB_ORDER_REVERSE (1 << 11) > >>> + > >>> /* FIMD Version 8 register offset definitions */ > >>> #define FIMD_V8_VIDTCON0 0x20010 > >>> #define FIMD_V8_VIDTCON1 0x20014 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3181C433EF for ; Fri, 25 Feb 2022 09:34:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LHMDr9Jro9CzYAcHHSBjp7Tj6ycVzHEL4FRhOdXg1So=; b=p+Jwofs2RpMHh1 duryGh5OyPpfrHAk0e5qx58JwE6lS/bEQ+OHDzdV0E7IAUf5b0EDH636343JQ612dFG2eVV5Svexm HTffPRaQsvWTaVbjAhrUlsfS/p7Q9t86Smg3NAJTjJnXIqaTlFR6gL3pm+Snqhg8xMONgAoItCxPK LKldlGv/7wSg6tV3JcGUgmon3UBTKSQM3Z9NPwcE/XB4gETC+3NnueFtoLmi43K1LXayRCmNLlvjY jVgI/rnr7m4yf/prI3939BW4pNvcweJcnkVFVitYxpnVAk29k5Gmv1iuKz2W/x8wWfNE2aT4oBBRb QqS4VTOpxsFVj/ZQ6JyQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nNWyY-004BdV-8C; Fri, 25 Feb 2022 09:33:22 +0000 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nNWyT-004Bci-VV for linux-arm-kernel@lists.infradead.org; Fri, 25 Feb 2022 09:33:20 +0000 Received: by mail-ej1-x634.google.com with SMTP id hw13so9602518ejc.9 for ; Fri, 25 Feb 2022 01:33:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to; bh=wVwXFGjPqrDDJSK8G4NlUrkX3LWHDibAAXwXLRr8zhU=; b=od9VIU2Y+YR/rihaLVf56h6HZXL6oQ2Xaazd0VFgMw8QYGgAtwLyQDY0Muby+Yxlc/ C49i+v7JiTmdK5Zz/kL9SWTClA2ZJ8MMY8DZzSk8XOr6f80uPnA0vXbNB2Y2lLkAHded rU2KFznU7l1zvoIQnWxt/1SzbePyI6aPZJlxfYD2euVRdW9GYTRj48BR1TGktN7w90pf 4Ntnn536n14uLsZPs0o3E2pwZl5z59kEVYEodgg4OCpznB1NOeHiaqJwbwG1JVF3F5oY UUoAJlfvkklglAqHXEE7+cO8lsSSE/2z8p2hEtDh2xruMeWHCFyOOqyWqMOoNwcjapcE VSxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=wVwXFGjPqrDDJSK8G4NlUrkX3LWHDibAAXwXLRr8zhU=; b=eN1e3g7SX43HFZfinwk8G+1k5zwPkJyK87KAS4zthwAxW2ruP7GR3uAHi9ZQGXvO4Y LkZP305eBlhlfJYsF3CYYpIe63tuARgKhKX6VRLcONkBXahcpYK/395r7mo5UreRNnXo LUvihf4z5hx5gWDAgNKgoAPyMtt03Et0QYuG0Tcfk8vbil/GthIXMpobNo04uT7GsgNF CidqtU1oI2RWY/OZQ3BR4/TtvnvE+IcglChhZu4vNNnA9KiV7kVMk9bBHTvmPYn3V7qU RQ+LqaAphE77aubUVQWFCgpKRQA9zMu8NBlwFPeo8SHD9ccMaWsJDgWpIyOZ1Z3HHaVt HEcg== X-Gm-Message-State: AOAM53315QiOxP0qPMo9pt1DwlwjBxFCFyHX5CZYzcxFl0U/dMs52iO8 UccbH8rYCo8eJ42b7Jz9FJw= X-Google-Smtp-Source: ABdhPJw6q7dLehrGphqLcggKl5vFOrSHQbhv9gy7yZjIFRQu0S1kAZvDLVs/+c2kVkSb2by7JkxMjQ== X-Received: by 2002:a17:907:75fc:b0:6d5:c6bd:6fbd with SMTP id jz28-20020a17090775fc00b006d5c6bd6fbdmr5383036ejc.695.1645781596237; Fri, 25 Feb 2022 01:33:16 -0800 (PST) Received: from adroid (027-177-184-091.ip-addr.vsenet.de. [91.184.177.27]) by smtp.gmail.com with ESMTPSA id f20-20020a170906739400b006ccc4eb357dsm808195ejl.8.2022.02.25.01.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Feb 2022 01:33:15 -0800 (PST) Date: Fri, 25 Feb 2022 10:33:13 +0100 From: Martin =?iso-8859-1?Q?J=FCcker?= To: Inki Dae Cc: Joonyoung Shim , Seung-Woo Kim , Kyungmin Park , David Airlie , Daniel Vetter , Krzysztof Kozlowski , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Martin =?iso-8859-1?Q?J=FCcker?= Subject: Re: [PATCH] drm/exynos: fimd: add BGR support for exynos4/5 Message-ID: <20220225093313.GA87542@adroid> References: <20220129220153.GA33165@adroid> <5e18705f-79c1-18a7-57f2-74866abe21e9@samsung.com> <20220224232723.GA133007@adroid> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220225_013318_050541_83A44101 X-CRM114-Status: GOOD ( 55.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SGVsbG8gSW5raSwKCk9uIEZyaSwgRmViIDI1LCAyMDIyIGF0IDEyOjUyOjU2UE0gKzA5MDAsIElu a2kgRGFlIHdyb3RlOgo+IEhpIE1hcnRpbiwKPiAKPiAyMi4gMi4gMjUuIDA4OjI37JeQIE1hcnRp biBKw7xja2VyIOydtCjqsIApIOyTtCDquIA6Cj4gPiBIZWxsbyBJbmtpLAo+ID4gCj4gPiBPbiBU aHUsIEZlYiAyNCwgMjAyMiBhdCAxMDo0MTowNEFNICswOTAwLCBJbmtpIERhZSB3cm90ZToKPiA+ PiBIaSBNYXJ0aW4uCj4gPj4KPiA+PiBJIGZvdW5kIHRoYXQgZXh5bm9zNCBhbmQgNSBkYXRhIHNo ZWV0IGluY2x1ZGUgZG9jdW1lbnRlZCBzYW1lIHJlZ2lzdGVyLgo+ID4+IFJHQl9PUkRFUl9FIGZp ZWxkIG9mIFZJRENPTnggcmVnaXN0ZXJzIHdpbGwgZG8gc2FtZSB0aGluZy4KPiA+IAo+ID4gSWYg SSByZWFkIHRoZSBtYW51YWwgY29ycmVjdGx5LCB0aGlzIHJlZ2lzdGVyIGNvbWJpbmVkIHdpdGgg dGhlCj4gPiBSR0JfT1JERVJfTyBtYWtlcyBpdCBwb3NzaWJsZSB0byBtYXAgdGhlIHdob2xlIFJH QiBpbnRlcmZhY2Ugb3V0cHV0IHRvIGEKPiA+IGRpZmZlcmVudCBvcmRlci4gV2hhdCBteSBwYXRj aCBwcm92aWRlcyBpcyBhIHdheSB0byBjb25maWd1cmUgZWFjaAo+ID4gaGFyZHdhcmUgcGxhbmUg c2VwYXJhdGVseSB3aGlsZSBtYWludGFpbmluZyBhIGNvbnNpc3RlbnQgb3V0cHV0IG9uIHRoZQo+ ID4gUkdCIGludGVyZmFjZS4KPiA+IAo+IAo+IFVuZGVyc3Rvb2QuIFlvdXIgcGF0Y2ggd2lsbCBh bGxvdyBCR1IgcGl4ZWwgb3JkZXIgcGVyIGEgcGxhbmUuIFNlZW1zIHRvIGJlIHVzZWZ1bCBiZWNh dXNlIGEgZnJhbWVidWZmZXIgd2l0aCBCR1IgcGl4ZWwgZm9ybWF0IGNhbiBiZSBkaXNwbGF5ZWQg b24gc2NyZWVuIHdpdGhvdXQgYW55IGNvbG9yIHNwYWNlIGNvbnZlcnNpb24uIDopCj4gCj4gPiBJ bXBsZW1lbnRpbmcgdGhlIFJHQl9PUkRFUl9PIGFuZCBFIHdvdWxkIG5lZWQgc29tZSBsb2dpYyB0 byBtYWtlIHN1cmUKPiA+IHRoYXQgYWxsIHBsYW5lcyBhcmUgYWx3YXlzIHVzaW5nIHRoZSBzYW1l IFJHQiBvcmRlci4KPiA+IAo+ID4+Cj4gPj4gSSdtIG5vdCBzdXJlIHdoZXRoZXIgdGhlIHVzZSBv ZiB1bmRvY3VtZW50ZWQgcmVnaXN0ZXIgaXMgc2FmZSBvciBub3QgLSBtYXliZSBzb21lIEhXIGJ1 ZyBleGlzdHMuCj4gPiAKPiA+IEkgc2VlLCB0aGF0IG1ha2VzIHNlbnNlLiBXb3VsZCBpdCBiZSBw b3NzaWJsZSB0aGVuIHRvIGludHJvZHVjZSBhIG5ldwo+ID4gY29tcGF0aWJsZSwgZS5nLiBzYW1z dW5nLGV4eW5vczQyMTAtZmltZC1leHQgd2hpY2ggY2FuIGJlIHVzZWQgb24gdGVzdGVkCj4gCj4g U2VlbXMgcHJvdmlkaW5nIGEgbmV3IGNvbXBhdGlibGUgaXMgbm90IGEgZ29vZCBpZGVhLgo+IAo+ ID4gZGV2aWNlcz8gSSBrbm93IHRoYXQgc29tZSBvdGhlciBHYWxheHkgTm90ZSBhbmQgUyBkZXZp Y2VzIHdpdGggdGhlCj4gPiBleHlub3M0IGNoaXAgaGF2ZSB0aGUgc2FtZSBwcm9ibGVtIChhbmQg c29sdXRpb24pLgo+IAo+IENvdWxkIHlvdSBnaXZlIG1lIG1vcmUgZGV0YWlscyBhYm91dCB0aGUg c2FtZSBwcm9ibGVtIGFuZCBpdHMgc29sdXRpb24gb24gdGhlIGRldmljZXM/Cj4gSXQgd291bGQg YmUgdXNlZnVsIGZvciB1cyB0byBkZWNpZGUgdGhlIHVwc3RyZWFtIGRpcmVjdGlvbi4KPgo+IElm IG5lY2Vzc2FyeSB0aGVuIHdlIG1heSBuZWVkIHRvIGNvbnRhY3QgSFcgZW5naW5lZXIgZm9yIGNs YXJpdHkuCgpIZXJlIGlzIG15IGN1cnJlbnQgdW5kZXJzdGFuZGluZyBvZiB0aGUgc2l0dWF0aW9u OgoKVGhlIGlzc3VlIGlzIHJlbGF0ZWQgdG8gQW5kcm9pZCBhbmQgYSByZWNvdmVyeSBpbWFnZSBo YXZpbmcgY29uZmxpY3RpbmcKcGl4ZWwgZm9ybWF0cyBvbiB0aGUgc2FtZSBkZXZpY2UuIFRoZXJl IGlzIGEgc29sdXRpb24gaW4gUmVwbGljYW50WzFdCmZvciB0aGlzIHVzaW5nIHBhcmFtZXRlcnMg Zm9yIHRoZSBmaW1kIGRyaXZlciB0byBmb3JjZSB0aGUgcGl4ZWwgZm9ybWF0CnRvIFJHQiBvciBC R1IuIEl0J3MgdXNpbmcgdGhlIFBOUk1PREUgcmVnaXN0ZXIgb24gVklEQ09OMCwgYnV0IHRoaXMK c29sdXRpb24gbmVlZHMgdHdvIHNlcGFyYXRlIGtlcm5lbHMgdG8gYmUgYnVpbHQgdG8gYWRkIHRo ZSBwYXJhbWV0ZXIgYXMKdGhlIGJvb3QgbG9hZGVyIGlzIG5vdCBhZGp1c3RhYmxlLgoKVGhpcyB3 YXMgYWxzbyBkaXNjdXNzZWQgaW4gZHJpLWRldmVsIGlyYyBhbmQgaXQgd2FzIHByb3Bvc2VkIHRv IGV4cG9zZQpib3RoIGZvcm1hdHMgYW5kIGZhaWwgdGhlIGF0b21pYyBjb21taXQgaWYgdXNlcnNw YWNlIHRyaWVkIHRvIHVzZSBib3RoClJHQiBhbmQgQkdSIGZvcm1hdHMgYXQgdGhlIHNhbWUgdGlt ZS4gV2l0aCB0aGlzIGFwcHJvYWNoIHRoZXJlIHNob3VsZCBiZQpzb21ldGhpbmcgb24gdGhlIHNj cmVlbiBidXQgaXQgbWlnaHQgaGFwcGVuIHRoYXQgc29tZSB1c2VycyBjYW4ndCBkZWFsCndpdGgg dGhlIGZhaWxpbmcgY29tbWl0cyBhcyBpdCdzIHJhdGhlciBkaWZmaWN1bHQgdG8gZmluZCB0aGUg Y2F1c2UgYW5kCmZpeCBpdCBvbiB0aGUgZ28uCgpBZnRlciB0aGF0IEkgYWNjaWRlbnRhbGx5IGRp c2NvdmVyZWQgdGhpcyB1bmRvY3VtZW50ZWQgcmVnaXN0ZXIgd2hpbGUKcmVhZGluZyB0aGUgb2xk IHZlbmRvciBzb3VyY2VzIGFuZCBpdCBzZWVtcyB0aGF0IGl0IGZpeGVzIGFsbCB0aGUKaXNzdWVz LiBBdCBsZWFzdCBpZiB0aGVyZSBhcmUgbm8gSFcgYnVncyBhcyB5b3UgbWVudGlvbmVkLgoKS2lu ZCBSZWdhcmRzCk1hcnRpbgoKWzFdIGh0dHBzOi8vZ2l0LnJlcGxpY2FudC51cy9yZXBsaWNhbnQt bmV4dC9rZXJuZWxfcmVwbGljYW50X2xpbnV4L2NvbW1pdC8/aD1yZXBsaWNhbnQtMTEmaWQ9Y2M1 YTA2MTViNDBjZDVlZGUxZWI4N2E2MGRhYTUwMzMzNzAxYTEzNQoKPiAKPiBUaGFua3MsCj4gSW5r aSBEYWUKPiAKPiA+IAo+ID4+Cj4gPj4gQW55d2F5LCBJJ2QgbGlrZSB0byByZWNvbW1lbmQgeW91 IHRvIHVzZSBkb2N1bWVudGVkIHJlZ2lzdGVyIG9ubHkuCj4gPj4KPiA+PiBTb3JyeSBmb3IgbGF0 ZSBhbmQgdGhhbmtzLAo+ID4+IElua2kgRGFlCj4gPiAKPiA+IEtpbmQgUmVnYXJkcwo+ID4gTWFy dGluCj4gPiAKPiA+Pgo+ID4+IDIyLiAxLiAzMC4gMDc6MDHsl5AgTWFydGluIErDvGNrZXIg7J20 KOqwgCkg7JO0IOq4gDoKPiA+Pj4gSW4gdGhlIGRvd25zdHJlYW0ga2VybmVscyBmb3IgZXh5bm9z NCBhbmQgZXh5bm9zNSBkZXZpY2VzLCB0aGVyZSBpcyBhbgo+ID4+PiB1bmRvY3VtZW50ZWQgcmVn aXN0ZXIgdGhhdCBjb250cm9scyB0aGUgb3JkZXIgb2YgdGhlIFJHQiBvdXRwdXQuIEl0IGNhbgo+ ID4+PiBiZSBzZXQgdG8gZWl0aGVyIG5vcm1hbCBvcmRlciBvciByZXZlcnNlZCwgd2hpY2ggZW5h YmxlcyBCR1Igc3VwcG9ydCBmb3IKPiA+Pj4gdGhvc2UgU29Dcy4KPiA+Pj4KPiA+Pj4gVGhpcyBw YXRjaCBlbmFibGVzIHRoZSBCR1Igc3VwcG9ydCBmb3IgYWxsIHRoZSBTb0NzIHRoYXQgd2VyZSBm b3VuZCB0bwo+ID4+PiBoYXZlIGF0IGxlYXN0IG9uZSBkZXZpY2Ugd2l0aCB0aGlzIGxvZ2ljIGlu IHRoZSBjb3JyZXNwb25kaW5nIGRvd25zdHJlYW0KPiA+Pj4ga2VybmVscy4KPiA+Pj4KPiA+Pj4g U2lnbmVkLW9mZi1ieTogTWFydGluIErDvGNrZXIgPG1hcnRpbi5qdWVja2VyQGdtYWlsLmNvbT4K PiA+Pj4gLS0tCj4gPj4+ICBkcml2ZXJzL2dwdS9kcm0vZXh5bm9zL2V4eW5vc19kcm1fZmltZC5j IHwgNDIgKysrKysrKysrKysrKysrKysrKysrKy0tCj4gPj4+ICBpbmNsdWRlL3ZpZGVvL3NhbXN1 bmdfZmltZC5oICAgICAgICAgICAgIHwgIDQgKysrCj4gPj4+ICAyIGZpbGVzIGNoYW5nZWQsIDQ0 IGluc2VydGlvbnMoKyksIDIgZGVsZXRpb25zKC0pCj4gPj4+Cj4gPj4+IGRpZmYgLS1naXQgYS9k cml2ZXJzL2dwdS9kcm0vZXh5bm9zL2V4eW5vc19kcm1fZmltZC5jIGIvZHJpdmVycy9ncHUvZHJt L2V4eW5vcy9leHlub3NfZHJtX2ZpbWQuYwo+ID4+PiBpbmRleCBjNzM1ZTUzOTM5ZDguLmNiNjMy MzYwYzk2OCAxMDA2NDQKPiA+Pj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL2V4eW5vcy9leHlub3Nf ZHJtX2ZpbWQuYwo+ID4+PiArKysgYi9kcml2ZXJzL2dwdS9kcm0vZXh5bm9zL2V4eW5vc19kcm1f ZmltZC5jCj4gPj4+IEBAIC0xMDksNiArMTA5LDcgQEAgc3RydWN0IGZpbWRfZHJpdmVyX2RhdGEg ewo+ID4+PiAgCXVuc2lnbmVkIGludCBoYXNfZHBfY2xrOjE7Cj4gPj4+ICAJdW5zaWduZWQgaW50 IGhhc19od190cmlnZ2VyOjE7Cj4gPj4+ICAJdW5zaWduZWQgaW50IGhhc190cmlnZ2VyX3Blcl90 ZToxOwo+ID4+PiArCXVuc2lnbmVkIGludCBoYXNfYmdyX3N1cHBvcnQ6MTsKPiA+Pj4gIH07Cj4g Pj4+ICAKPiA+Pj4gIHN0YXRpYyBzdHJ1Y3QgZmltZF9kcml2ZXJfZGF0YSBzM2M2NHh4X2ZpbWRf ZHJpdmVyX2RhdGEgPSB7Cj4gPj4+IEBAIC0xMzgsNiArMTM5LDcgQEAgc3RhdGljIHN0cnVjdCBm aW1kX2RyaXZlcl9kYXRhIGV4eW5vczRfZmltZF9kcml2ZXJfZGF0YSA9IHsKPiA+Pj4gIAkubGNk YmxrX2J5cGFzc19zaGlmdCA9IDEsCj4gPj4+ICAJLmhhc19zaGFkb3djb24gPSAxLAo+ID4+PiAg CS5oYXNfdnRzZWwgPSAxLAo+ID4+PiArCS5oYXNfYmdyX3N1cHBvcnQgPSAxLAo+ID4+PiAgfTsK PiA+Pj4gIAo+ID4+PiAgc3RhdGljIHN0cnVjdCBmaW1kX2RyaXZlcl9kYXRhIGV4eW5vczVfZmlt ZF9kcml2ZXJfZGF0YSA9IHsKPiA+Pj4gQEAgLTE0OSw2ICsxNTEsNyBAQCBzdGF0aWMgc3RydWN0 IGZpbWRfZHJpdmVyX2RhdGEgZXh5bm9zNV9maW1kX2RyaXZlcl9kYXRhID0gewo+ID4+PiAgCS5o YXNfdmlkb3V0Y29uID0gMSwKPiA+Pj4gIAkuaGFzX3Z0c2VsID0gMSwKPiA+Pj4gIAkuaGFzX2Rw X2NsayA9IDEsCj4gPj4+ICsJLmhhc19iZ3Jfc3VwcG9ydCA9IDEsCj4gPj4+ICB9Owo+ID4+PiAg Cj4gPj4+ICBzdGF0aWMgc3RydWN0IGZpbWRfZHJpdmVyX2RhdGEgZXh5bm9zNTQyMF9maW1kX2Ry aXZlcl9kYXRhID0gewo+ID4+PiBAQCAtMTYyLDYgKzE2NSw3IEBAIHN0YXRpYyBzdHJ1Y3QgZmlt ZF9kcml2ZXJfZGF0YSBleHlub3M1NDIwX2ZpbWRfZHJpdmVyX2RhdGEgPSB7Cj4gPj4+ICAJLmhh c192dHNlbCA9IDEsCj4gPj4+ICAJLmhhc19taWNfYnlwYXNzID0gMSwKPiA+Pj4gIAkuaGFzX2Rw X2NsayA9IDEsCj4gPj4+ICsJLmhhc19iZ3Jfc3VwcG9ydCA9IDEsCj4gPj4+ICB9Owo+ID4+PiAg Cj4gPj4+ICBzdHJ1Y3QgZmltZF9jb250ZXh0IHsKPiA+Pj4gQEAgLTIyNiw2ICsyMzAsMTggQEAg c3RhdGljIGNvbnN0IHVpbnQzMl90IGZpbWRfZm9ybWF0c1tdID0gewo+ID4+PiAgCURSTV9GT1JN QVRfQVJHQjg4ODgsCj4gPj4+ICB9Owo+ID4+PiAgCj4gPj4+ICtzdGF0aWMgY29uc3QgdWludDMy X3QgZmltZF9leHRlbmRlZF9mb3JtYXRzW10gPSB7Cj4gPj4+ICsJRFJNX0ZPUk1BVF9DOCwKPiA+ Pj4gKwlEUk1fRk9STUFUX1hSR0IxNTU1LAo+ID4+PiArCURSTV9GT1JNQVRfWEJHUjE1NTUsCj4g Pj4+ICsJRFJNX0ZPUk1BVF9SR0I1NjUsCj4gPj4+ICsJRFJNX0ZPUk1BVF9CR1I1NjUsCj4gPj4+ ICsJRFJNX0ZPUk1BVF9YUkdCODg4OCwKPiA+Pj4gKwlEUk1fRk9STUFUX1hCR1I4ODg4LAo+ID4+ PiArCURSTV9GT1JNQVRfQVJHQjg4ODgsCj4gPj4+ICsJRFJNX0ZPUk1BVF9BQkdSODg4OCwKPiA+ Pj4gK307Cj4gPj4+ICsKPiA+Pj4gIHN0YXRpYyBjb25zdCB1bnNpZ25lZCBpbnQgY2FwYWJpbGl0 aWVzW1dJTkRPV1NfTlJdID0gewo+ID4+PiAgCTAsCj4gPj4+ICAJRVhZTk9TX0RSTV9QTEFORV9D QVBfV0lOX0JMRU5EIHwgRVhZTk9TX0RSTV9QTEFORV9DQVBfUElYX0JMRU5ELAo+ID4+PiBAQCAt NjczLDIxICs2ODksMjUgQEAgc3RhdGljIHZvaWQgZmltZF93aW5fc2V0X3BpeGZtdChzdHJ1Y3Qg ZmltZF9jb250ZXh0ICpjdHgsIHVuc2lnbmVkIGludCB3aW4sCj4gPj4+ICAJCXZhbCB8PSBXSU5D T054X0JZVFNXUDsKPiA+Pj4gIAkJYnJlYWs7Cj4gPj4+ICAJY2FzZSBEUk1fRk9STUFUX1hSR0Ix NTU1Ogo+ID4+PiArCWNhc2UgRFJNX0ZPUk1BVF9YQkdSMTU1NToKPiA+Pj4gIAkJdmFsIHw9IFdJ TkNPTjBfQlBQTU9ERV8xNkJQUF8xNTU1Owo+ID4+PiAgCQl2YWwgfD0gV0lOQ09OeF9IQVdTV1A7 Cj4gPj4+ICAJCXZhbCB8PSBXSU5DT054X0JVUlNUTEVOXzE2V09SRDsKPiA+Pj4gIAkJYnJlYWs7 Cj4gPj4+ICAJY2FzZSBEUk1fRk9STUFUX1JHQjU2NToKPiA+Pj4gKwljYXNlIERSTV9GT1JNQVRf QkdSNTY1Ogo+ID4+PiAgCQl2YWwgfD0gV0lOQ09OMF9CUFBNT0RFXzE2QlBQXzU2NTsKPiA+Pj4g IAkJdmFsIHw9IFdJTkNPTnhfSEFXU1dQOwo+ID4+PiAgCQl2YWwgfD0gV0lOQ09OeF9CVVJTVExF Tl8xNldPUkQ7Cj4gPj4+ICAJCWJyZWFrOwo+ID4+PiAgCWNhc2UgRFJNX0ZPUk1BVF9YUkdCODg4 ODoKPiA+Pj4gKwljYXNlIERSTV9GT1JNQVRfWEJHUjg4ODg6Cj4gPj4+ICAJCXZhbCB8PSBXSU5D T04wX0JQUE1PREVfMjRCUFBfODg4Owo+ID4+PiAgCQl2YWwgfD0gV0lOQ09OeF9XU1dQOwo+ID4+ PiAgCQl2YWwgfD0gV0lOQ09OeF9CVVJTVExFTl8xNldPUkQ7Cj4gPj4+ICAJCWJyZWFrOwo+ID4+ PiAgCWNhc2UgRFJNX0ZPUk1BVF9BUkdCODg4ODoKPiA+Pj4gKwljYXNlIERSTV9GT1JNQVRfQUJH Ujg4ODg6Cj4gPj4+ICAJZGVmYXVsdDoKPiA+Pj4gIAkJdmFsIHw9IFdJTkNPTjFfQlBQTU9ERV8y NUJQUF9BMTg4ODsKPiA+Pj4gIAkJdmFsIHw9IFdJTkNPTnhfV1NXUDsKPiA+Pj4gQEAgLTY5NSw2 ICs3MTUsMTggQEAgc3RhdGljIHZvaWQgZmltZF93aW5fc2V0X3BpeGZtdChzdHJ1Y3QgZmltZF9j b250ZXh0ICpjdHgsIHVuc2lnbmVkIGludCB3aW4sCj4gPj4+ICAJCWJyZWFrOwo+ID4+PiAgCX0K PiA+Pj4gIAo+ID4+PiArCXN3aXRjaCAocGl4ZWxfZm9ybWF0KSB7Cj4gPj4+ICsJY2FzZSBEUk1f Rk9STUFUX1hCR1IxNTU1Ogo+ID4+PiArCWNhc2UgRFJNX0ZPUk1BVF9YQkdSODg4ODoKPiA+Pj4g KwljYXNlIERSTV9GT1JNQVRfQUJHUjg4ODg6Cj4gPj4+ICsJY2FzZSBEUk1fRk9STUFUX0JHUjU2 NToKPiA+Pj4gKwkJd3JpdGVsKFdJTl9SR0JfT1JERVJfUkVWRVJTRSwgY3R4LT5yZWdzICsgV0lO X1JHQl9PUkRFUih3aW4pKTsKPiA+Pj4gKwkJYnJlYWs7Cj4gPj4+ICsJZGVmYXVsdDoKPiA+Pj4g KwkJd3JpdGVsKFdJTl9SR0JfT1JERVJfRk9SV0FSRCwgY3R4LT5yZWdzICsgV0lOX1JHQl9PUkRF Uih3aW4pKTsKPiA+Pj4gKwkJYnJlYWs7Cj4gPj4+ICsJfQo+ID4+PiArCj4gPj4+ICAJLyoKPiA+ Pj4gIAkgKiBTZXR0aW5nIGRtYS1idXJzdCB0byAxNldvcmQgY2F1c2VzIHBlcm1hbmVudCB0ZWFy aW5nIGZvciB2ZXJ5IHNtYWxsCj4gPj4+ICAJICogYnVmZmVycywgZS5nLiBjdXJzb3IgYnVmZmVy LiBCdXJzdCBNb2RlIHN3aXRjaGluZyB3aGljaCBiYXNlZCBvbgo+ID4+PiBAQCAtMTA3NCw4ICsx MTA2LDE0IEBAIHN0YXRpYyBpbnQgZmltZF9iaW5kKHN0cnVjdCBkZXZpY2UgKmRldiwgc3RydWN0 IGRldmljZSAqbWFzdGVyLCB2b2lkICpkYXRhKQo+ID4+PiAgCWN0eC0+ZHJtX2RldiA9IGRybV9k ZXY7Cj4gPj4+ICAKPiA+Pj4gIAlmb3IgKGkgPSAwOyBpIDwgV0lORE9XU19OUjsgaSsrKSB7Cj4g Pj4+IC0JCWN0eC0+Y29uZmlnc1tpXS5waXhlbF9mb3JtYXRzID0gZmltZF9mb3JtYXRzOwo+ID4+ PiAtCQljdHgtPmNvbmZpZ3NbaV0ubnVtX3BpeGVsX2Zvcm1hdHMgPSBBUlJBWV9TSVpFKGZpbWRf Zm9ybWF0cyk7Cj4gPj4+ICsJCWlmIChjdHgtPmRyaXZlcl9kYXRhLT5oYXNfYmdyX3N1cHBvcnQp IHsKPiA+Pj4gKwkJCWN0eC0+Y29uZmlnc1tpXS5waXhlbF9mb3JtYXRzID0gZmltZF9leHRlbmRl ZF9mb3JtYXRzOwo+ID4+PiArCQkJY3R4LT5jb25maWdzW2ldLm51bV9waXhlbF9mb3JtYXRzID0g QVJSQVlfU0laRShmaW1kX2V4dGVuZGVkX2Zvcm1hdHMpOwo+ID4+PiArCQl9IGVsc2Ugewo+ID4+ PiArCQkJY3R4LT5jb25maWdzW2ldLnBpeGVsX2Zvcm1hdHMgPSBmaW1kX2Zvcm1hdHM7Cj4gPj4+ ICsJCQljdHgtPmNvbmZpZ3NbaV0ubnVtX3BpeGVsX2Zvcm1hdHMgPSBBUlJBWV9TSVpFKGZpbWRf Zm9ybWF0cyk7Cj4gPj4+ICsJCX0KPiA+Pj4gKwo+ID4+PiAgCQljdHgtPmNvbmZpZ3NbaV0uenBv cyA9IGk7Cj4gPj4+ICAJCWN0eC0+Y29uZmlnc1tpXS50eXBlID0gZmltZF93aW5fdHlwZXNbaV07 Cj4gPj4+ICAJCWN0eC0+Y29uZmlnc1tpXS5jYXBhYmlsaXRpZXMgPSBjYXBhYmlsaXRpZXNbaV07 Cj4gPj4+IGRpZmYgLS1naXQgYS9pbmNsdWRlL3ZpZGVvL3NhbXN1bmdfZmltZC5oIGIvaW5jbHVk ZS92aWRlby9zYW1zdW5nX2ZpbWQuaAo+ID4+PiBpbmRleCBjNGE5M2NlMWRlNDguLmU2OTY2ZDE4 NzU5MSAxMDA2NDQKPiA+Pj4gLS0tIGEvaW5jbHVkZS92aWRlby9zYW1zdW5nX2ZpbWQuaAo+ID4+ PiArKysgYi9pbmNsdWRlL3ZpZGVvL3NhbXN1bmdfZmltZC5oCj4gPj4+IEBAIC00NzYsNiArNDc2 LDEwIEBACj4gPj4+ICAgKiAxMTExCQktbm9uZS0JIC1ub25lLSAgIC1ub25lLSAgIC1ub25lLSAg ICAtbm9uZS0KPiA+Pj4gICovCj4gPj4+ICAKPiA+Pj4gKyNkZWZpbmUgV0lOX1JHQl9PUkRFUihf d2luKQkJCSgweDIwMjAgKyAoKF93aW4pICogNCkpCj4gPj4+ICsjZGVmaW5lIFdJTl9SR0JfT1JE RVJfRk9SV0FSRAkJCSgwIDw8IDExKQo+ID4+PiArI2RlZmluZSBXSU5fUkdCX09SREVSX1JFVkVS U0UJCQkoMSA8PCAxMSkKPiA+Pj4gKwo+ID4+PiAgLyogRklNRCBWZXJzaW9uIDggcmVnaXN0ZXIg b2Zmc2V0IGRlZmluaXRpb25zICovCj4gPj4+ICAjZGVmaW5lIEZJTURfVjhfVklEVENPTjAJMHgy MDAxMAo+ID4+PiAgI2RlZmluZSBGSU1EX1Y4X1ZJRFRDT04xCTB4MjAwMTQKPiA+IAoKX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5l bCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6 Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DEBCDC433F5 for ; Sat, 26 Feb 2022 10:01:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2B8BA10ECF7; Sat, 26 Feb 2022 10:01:01 +0000 (UTC) Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by gabe.freedesktop.org (Postfix) with ESMTPS id F2B5C10E774 for ; Fri, 25 Feb 2022 09:33:17 +0000 (UTC) Received: by mail-ej1-x62d.google.com with SMTP id qk11so9691468ejb.2 for ; Fri, 25 Feb 2022 01:33:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to; bh=wVwXFGjPqrDDJSK8G4NlUrkX3LWHDibAAXwXLRr8zhU=; b=od9VIU2Y+YR/rihaLVf56h6HZXL6oQ2Xaazd0VFgMw8QYGgAtwLyQDY0Muby+Yxlc/ C49i+v7JiTmdK5Zz/kL9SWTClA2ZJ8MMY8DZzSk8XOr6f80uPnA0vXbNB2Y2lLkAHded rU2KFznU7l1zvoIQnWxt/1SzbePyI6aPZJlxfYD2euVRdW9GYTRj48BR1TGktN7w90pf 4Ntnn536n14uLsZPs0o3E2pwZl5z59kEVYEodgg4OCpznB1NOeHiaqJwbwG1JVF3F5oY UUoAJlfvkklglAqHXEE7+cO8lsSSE/2z8p2hEtDh2xruMeWHCFyOOqyWqMOoNwcjapcE VSxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=wVwXFGjPqrDDJSK8G4NlUrkX3LWHDibAAXwXLRr8zhU=; b=l+TcR1XURtfKjoGlACJKeeEPW2yHmuw9B+R3TZU7zJiYEBoCUesHyED7nPWvMYU4Z/ pWunqfJl8NpC5iLoHi+5E174AsB5sZqI+Q/PNj5Cj6SDP6imiCOHjo9/OqG2583EMf3f wxJtkQ0dM1/m7ozsNZLWhWfrdq8+5XadRA7HMsNxQDsE71whhDoFq2wb18/JxEMzElM3 dE8MjXjCmzbqQTh/eY2fRVywnyLkJP+u56NJjFC+SqMegaWcH4NohV54+VmXuV2kcTqD nzrxCS2pIXGMZeR8ERVWznRwXLZS1QX7Kzm21VCr+aC3NgrlQzGnEOCPYyny8229o3zx ny2Q== X-Gm-Message-State: AOAM533Vvlvj0ZdE4Fnkly9/Dz3c7007O4j+hTeicDCXHLW5miPytiIN yM6+SbgWWPnUUtr54pr3btfeOiKCYogJZw== X-Google-Smtp-Source: ABdhPJw6q7dLehrGphqLcggKl5vFOrSHQbhv9gy7yZjIFRQu0S1kAZvDLVs/+c2kVkSb2by7JkxMjQ== X-Received: by 2002:a17:907:75fc:b0:6d5:c6bd:6fbd with SMTP id jz28-20020a17090775fc00b006d5c6bd6fbdmr5383036ejc.695.1645781596237; Fri, 25 Feb 2022 01:33:16 -0800 (PST) Received: from adroid (027-177-184-091.ip-addr.vsenet.de. [91.184.177.27]) by smtp.gmail.com with ESMTPSA id f20-20020a170906739400b006ccc4eb357dsm808195ejl.8.2022.02.25.01.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Feb 2022 01:33:15 -0800 (PST) Date: Fri, 25 Feb 2022 10:33:13 +0100 From: Martin =?iso-8859-1?Q?J=FCcker?= To: Inki Dae Subject: Re: [PATCH] drm/exynos: fimd: add BGR support for exynos4/5 Message-ID: <20220225093313.GA87542@adroid> References: <20220129220153.GA33165@adroid> <5e18705f-79c1-18a7-57f2-74866abe21e9@samsung.com> <20220224232723.GA133007@adroid> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Mailman-Approved-At: Sat, 26 Feb 2022 10:00:59 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-samsung-soc@vger.kernel.org, Joonyoung Shim , Krzysztof Kozlowski , David Airlie , Seung-Woo Kim , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Kyungmin Park , Martin =?iso-8859-1?Q?J=FCcker?= , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hello Inki, On Fri, Feb 25, 2022 at 12:52:56PM +0900, Inki Dae wrote: > Hi Martin, > > 22. 2. 25. 08:27에 Martin Jücker 이(가) 쓴 글: > > Hello Inki, > > > > On Thu, Feb 24, 2022 at 10:41:04AM +0900, Inki Dae wrote: > >> Hi Martin. > >> > >> I found that exynos4 and 5 data sheet include documented same register. > >> RGB_ORDER_E field of VIDCONx registers will do same thing. > > > > If I read the manual correctly, this register combined with the > > RGB_ORDER_O makes it possible to map the whole RGB interface output to a > > different order. What my patch provides is a way to configure each > > hardware plane separately while maintaining a consistent output on the > > RGB interface. > > > > Understood. Your patch will allow BGR pixel order per a plane. Seems to be useful because a framebuffer with BGR pixel format can be displayed on screen without any color space conversion. :) > > > Implementing the RGB_ORDER_O and E would need some logic to make sure > > that all planes are always using the same RGB order. > > > >> > >> I'm not sure whether the use of undocumented register is safe or not - maybe some HW bug exists. > > > > I see, that makes sense. Would it be possible then to introduce a new > > compatible, e.g. samsung,exynos4210-fimd-ext which can be used on tested > > Seems providing a new compatible is not a good idea. > > > devices? I know that some other Galaxy Note and S devices with the > > exynos4 chip have the same problem (and solution). > > Could you give me more details about the same problem and its solution on the devices? > It would be useful for us to decide the upstream direction. > > If necessary then we may need to contact HW engineer for clarity. Here is my current understanding of the situation: The issue is related to Android and a recovery image having conflicting pixel formats on the same device. There is a solution in Replicant[1] for this using parameters for the fimd driver to force the pixel format to RGB or BGR. It's using the PNRMODE register on VIDCON0, but this solution needs two separate kernels to be built to add the parameter as the boot loader is not adjustable. This was also discussed in dri-devel irc and it was proposed to expose both formats and fail the atomic commit if userspace tried to use both RGB and BGR formats at the same time. With this approach there should be something on the screen but it might happen that some users can't deal with the failing commits as it's rather difficult to find the cause and fix it on the go. After that I accidentally discovered this undocumented register while reading the old vendor sources and it seems that it fixes all the issues. At least if there are no HW bugs as you mentioned. Kind Regards Martin [1] https://git.replicant.us/replicant-next/kernel_replicant_linux/commit/?h=replicant-11&id=cc5a0615b40cd5ede1eb87a60daa50333701a135 > > Thanks, > Inki Dae > > > > >> > >> Anyway, I'd like to recommend you to use documented register only. > >> > >> Sorry for late and thanks, > >> Inki Dae > > > > Kind Regards > > Martin > > > >> > >> 22. 1. 30. 07:01에 Martin Jücker 이(가) 쓴 글: > >>> In the downstream kernels for exynos4 and exynos5 devices, there is an > >>> undocumented register that controls the order of the RGB output. It can > >>> be set to either normal order or reversed, which enables BGR support for > >>> those SoCs. > >>> > >>> This patch enables the BGR support for all the SoCs that were found to > >>> have at least one device with this logic in the corresponding downstream > >>> kernels. > >>> > >>> Signed-off-by: Martin Jücker > >>> --- > >>> drivers/gpu/drm/exynos/exynos_drm_fimd.c | 42 ++++++++++++++++++++++-- > >>> include/video/samsung_fimd.h | 4 +++ > >>> 2 files changed, 44 insertions(+), 2 deletions(-) > >>> > >>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c > >>> index c735e53939d8..cb632360c968 100644 > >>> --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c > >>> +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c > >>> @@ -109,6 +109,7 @@ struct fimd_driver_data { > >>> unsigned int has_dp_clk:1; > >>> unsigned int has_hw_trigger:1; > >>> unsigned int has_trigger_per_te:1; > >>> + unsigned int has_bgr_support:1; > >>> }; > >>> > >>> static struct fimd_driver_data s3c64xx_fimd_driver_data = { > >>> @@ -138,6 +139,7 @@ static struct fimd_driver_data exynos4_fimd_driver_data = { > >>> .lcdblk_bypass_shift = 1, > >>> .has_shadowcon = 1, > >>> .has_vtsel = 1, > >>> + .has_bgr_support = 1, > >>> }; > >>> > >>> static struct fimd_driver_data exynos5_fimd_driver_data = { > >>> @@ -149,6 +151,7 @@ static struct fimd_driver_data exynos5_fimd_driver_data = { > >>> .has_vidoutcon = 1, > >>> .has_vtsel = 1, > >>> .has_dp_clk = 1, > >>> + .has_bgr_support = 1, > >>> }; > >>> > >>> static struct fimd_driver_data exynos5420_fimd_driver_data = { > >>> @@ -162,6 +165,7 @@ static struct fimd_driver_data exynos5420_fimd_driver_data = { > >>> .has_vtsel = 1, > >>> .has_mic_bypass = 1, > >>> .has_dp_clk = 1, > >>> + .has_bgr_support = 1, > >>> }; > >>> > >>> struct fimd_context { > >>> @@ -226,6 +230,18 @@ static const uint32_t fimd_formats[] = { > >>> DRM_FORMAT_ARGB8888, > >>> }; > >>> > >>> +static const uint32_t fimd_extended_formats[] = { > >>> + DRM_FORMAT_C8, > >>> + DRM_FORMAT_XRGB1555, > >>> + DRM_FORMAT_XBGR1555, > >>> + DRM_FORMAT_RGB565, > >>> + DRM_FORMAT_BGR565, > >>> + DRM_FORMAT_XRGB8888, > >>> + DRM_FORMAT_XBGR8888, > >>> + DRM_FORMAT_ARGB8888, > >>> + DRM_FORMAT_ABGR8888, > >>> +}; > >>> + > >>> static const unsigned int capabilities[WINDOWS_NR] = { > >>> 0, > >>> EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, > >>> @@ -673,21 +689,25 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, > >>> val |= WINCONx_BYTSWP; > >>> break; > >>> case DRM_FORMAT_XRGB1555: > >>> + case DRM_FORMAT_XBGR1555: > >>> val |= WINCON0_BPPMODE_16BPP_1555; > >>> val |= WINCONx_HAWSWP; > >>> val |= WINCONx_BURSTLEN_16WORD; > >>> break; > >>> case DRM_FORMAT_RGB565: > >>> + case DRM_FORMAT_BGR565: > >>> val |= WINCON0_BPPMODE_16BPP_565; > >>> val |= WINCONx_HAWSWP; > >>> val |= WINCONx_BURSTLEN_16WORD; > >>> break; > >>> case DRM_FORMAT_XRGB8888: > >>> + case DRM_FORMAT_XBGR8888: > >>> val |= WINCON0_BPPMODE_24BPP_888; > >>> val |= WINCONx_WSWP; > >>> val |= WINCONx_BURSTLEN_16WORD; > >>> break; > >>> case DRM_FORMAT_ARGB8888: > >>> + case DRM_FORMAT_ABGR8888: > >>> default: > >>> val |= WINCON1_BPPMODE_25BPP_A1888; > >>> val |= WINCONx_WSWP; > >>> @@ -695,6 +715,18 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, > >>> break; > >>> } > >>> > >>> + switch (pixel_format) { > >>> + case DRM_FORMAT_XBGR1555: > >>> + case DRM_FORMAT_XBGR8888: > >>> + case DRM_FORMAT_ABGR8888: > >>> + case DRM_FORMAT_BGR565: > >>> + writel(WIN_RGB_ORDER_REVERSE, ctx->regs + WIN_RGB_ORDER(win)); > >>> + break; > >>> + default: > >>> + writel(WIN_RGB_ORDER_FORWARD, ctx->regs + WIN_RGB_ORDER(win)); > >>> + break; > >>> + } > >>> + > >>> /* > >>> * Setting dma-burst to 16Word causes permanent tearing for very small > >>> * buffers, e.g. cursor buffer. Burst Mode switching which based on > >>> @@ -1074,8 +1106,14 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) > >>> ctx->drm_dev = drm_dev; > >>> > >>> for (i = 0; i < WINDOWS_NR; i++) { > >>> - ctx->configs[i].pixel_formats = fimd_formats; > >>> - ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); > >>> + if (ctx->driver_data->has_bgr_support) { > >>> + ctx->configs[i].pixel_formats = fimd_extended_formats; > >>> + ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_extended_formats); > >>> + } else { > >>> + ctx->configs[i].pixel_formats = fimd_formats; > >>> + ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); > >>> + } > >>> + > >>> ctx->configs[i].zpos = i; > >>> ctx->configs[i].type = fimd_win_types[i]; > >>> ctx->configs[i].capabilities = capabilities[i]; > >>> diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h > >>> index c4a93ce1de48..e6966d187591 100644 > >>> --- a/include/video/samsung_fimd.h > >>> +++ b/include/video/samsung_fimd.h > >>> @@ -476,6 +476,10 @@ > >>> * 1111 -none- -none- -none- -none- -none- > >>> */ > >>> > >>> +#define WIN_RGB_ORDER(_win) (0x2020 + ((_win) * 4)) > >>> +#define WIN_RGB_ORDER_FORWARD (0 << 11) > >>> +#define WIN_RGB_ORDER_REVERSE (1 << 11) > >>> + > >>> /* FIMD Version 8 register offset definitions */ > >>> #define FIMD_V8_VIDTCON0 0x20010 > >>> #define FIMD_V8_VIDTCON1 0x20014 > >