diff for duplicates of <20220302024930.18758-4-tommy_huang@aspeedtech.com> diff --git a/a/1.txt b/N1/1.txt index bb9911f..feb43f3 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -65,3 +65,9 @@ index b53fee6f1c17..d4b56b3c7597 100644 priv->scan_line_max = config->scan_line_max; -- 2.17.1 + + +_______________________________________________ +linux-arm-kernel mailing list +linux-arm-kernel@lists.infradead.org +http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/a/content_digest b/N1/content_digest index 9466fdb..8bc0b45 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,7 +2,17 @@ "From\0Tommy Haung <tommy_huang@aspeedtech.com>\0" "Subject\0[PATCH v6 3/5] drm/aspeed: Update INTR_STS handling\0" "Date\0Wed, 2 Mar 2022 10:49:28 +0800\0" - "To\0linux-aspeed@lists.ozlabs.org\0" + "To\0<joel@jms.id.au>" + <airlied@linux.ie> + <daniel@ffwll.ch> + <robh+dt@kernel.org> + <andrew@aj.id.au> + <linux-aspeed@lists.ozlabs.org> + <dri-devel@lists.freedesktop.org> + <devicetree@vger.kernel.org> + <linux-arm-kernel@lists.infradead.org> + " <linux-kernel@vger.kernel.org>\0" + "Cc\0<BMC-SW@aspeedtech.com>\0" "\00:1\0" "b\0" "Add interrupt clear register define for further chip support.\n" @@ -71,6 +81,12 @@ " \tpriv->throd_val = config->throd_val;\n" " \tpriv->scan_line_max = config->scan_line_max;\n" "-- \n" - 2.17.1 + "2.17.1\n" + "\n" + "\n" + "_______________________________________________\n" + "linux-arm-kernel mailing list\n" + "linux-arm-kernel@lists.infradead.org\n" + http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -edac39bff8c3d9b8c9a35456c7866f58a1f4ba515151a274d2c48a4057c8d4ba +45de233f71ad000da98f7578826fd54a34daa1c9f850d864ec2f04c1c4ba79c6
diff --git a/a/content_digest b/N2/content_digest index 9466fdb..98cf370 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -2,7 +2,17 @@ "From\0Tommy Haung <tommy_huang@aspeedtech.com>\0" "Subject\0[PATCH v6 3/5] drm/aspeed: Update INTR_STS handling\0" "Date\0Wed, 2 Mar 2022 10:49:28 +0800\0" - "To\0linux-aspeed@lists.ozlabs.org\0" + "To\0<joel@jms.id.au>" + <airlied@linux.ie> + <daniel@ffwll.ch> + <robh+dt@kernel.org> + <andrew@aj.id.au> + <linux-aspeed@lists.ozlabs.org> + <dri-devel@lists.freedesktop.org> + <devicetree@vger.kernel.org> + <linux-arm-kernel@lists.infradead.org> + " <linux-kernel@vger.kernel.org>\0" + "Cc\0<BMC-SW@aspeedtech.com>\0" "\00:1\0" "b\0" "Add interrupt clear register define for further chip support.\n" @@ -73,4 +83,4 @@ "-- \n" 2.17.1 -edac39bff8c3d9b8c9a35456c7866f58a1f4ba515151a274d2c48a4057c8d4ba +5022f587fb71041bc0c4ed3bd5ff28fce3ff29c485e595e651992fff4c32c7a6
diff --git a/a/content_digest b/N3/content_digest index 9466fdb..8e9ba25 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -2,7 +2,17 @@ "From\0Tommy Haung <tommy_huang@aspeedtech.com>\0" "Subject\0[PATCH v6 3/5] drm/aspeed: Update INTR_STS handling\0" "Date\0Wed, 2 Mar 2022 10:49:28 +0800\0" - "To\0linux-aspeed@lists.ozlabs.org\0" + "To\0<joel@jms.id.au>" + <airlied@linux.ie> + <daniel@ffwll.ch> + <robh+dt@kernel.org> + <andrew@aj.id.au> + <linux-aspeed@lists.ozlabs.org> + <dri-devel@lists.freedesktop.org> + <devicetree@vger.kernel.org> + <linux-arm-kernel@lists.infradead.org> + " <linux-kernel@vger.kernel.org>\0" + "Cc\0BMC-SW@aspeedtech.com\0" "\00:1\0" "b\0" "Add interrupt clear register define for further chip support.\n" @@ -73,4 +83,4 @@ "-- \n" 2.17.1 -edac39bff8c3d9b8c9a35456c7866f58a1f4ba515151a274d2c48a4057c8d4ba +3fee3236d13e6546a25db428e8d157cc5906c201c221f80f852223560eb1ce80
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