From: Stephen Boyd <sboyd@kernel.org>
To: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>,
linux-clk@vger.kernel.org
Cc: git@xilinx.com, michal.simek@xilinx.com,
linux-kernel@vger.kernel.org,
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Subject: Re: [PATCH 2/2] clk: zynq: Update the parameters to zynq_clk_register_periph_clk
Date: Fri, 11 Mar 2022 18:26:26 -0800 [thread overview]
Message-ID: <20220312022628.3DFE7C340E9@smtp.kernel.org> (raw)
In-Reply-To: <20220222130903.17235-3-shubhrajyoti.datta@xilinx.com>
Quoting Shubhrajyoti Datta (2022-02-22 05:09:03)
> In case there are only one gate or the two_gate is 0 the clk1 clock
> passed is not used. We are passing 0 which is arm_pll.
> Pass a invalid clock instead.
>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> ---
Applied to clk-next
prev parent reply other threads:[~2022-03-12 2:26 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-22 13:09 [PATCH 0/2] clk: zynq: trivial fixes Shubhrajyoti Datta
2022-02-22 13:09 ` [PATCH 1/2] clk: zynq: trivial warning fix Shubhrajyoti Datta
2022-03-12 2:26 ` Stephen Boyd
2022-02-22 13:09 ` [PATCH 2/2] clk: zynq: Update the parameters to zynq_clk_register_periph_clk Shubhrajyoti Datta
2022-03-12 2:26 ` Stephen Boyd [this message]
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