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Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 46761a6fa8..5d7381c771 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -75,6 +75,10 @@ static RISCVException fs(CPURISCVState *env, int csrno) !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { return RISCV_EXCP_ILLEGAL_INST; } + + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { + return smstateen_acc_ok(env, PRV_U, SMSTATEEN0_FCSR); + } #endif return RISCV_EXCP_NONE; } @@ -2005,6 +2009,10 @@ static RISCVException write_mstateen(CPURISCVState *env, int csrno, uint64_t wr_mask = 1UL << SMSTATEEN_STATEN; reg = &env->mstateen[csrno - CSR_MSTATEEN0]; + if (riscv_has_ext(env, RVF)) { + wr_mask |= 1UL << SMSTATEEN0_FCSR; + } + write_smstateen(env, reg, wr_mask, new_val); return RISCV_EXCP_NONE; @@ -2028,6 +2036,10 @@ static RISCVException write_mstateenh(CPURISCVState *env, int csrno, reg = &env->mstateen[csrno - CSR_MSTATEEN0H - 0x10]; val = (uint64_t)new_val << 32; val |= *reg & 0xFFFFFFFF; + if (riscv_has_ext(env, RVF)) { + wr_mask |= 1UL << SMSTATEEN0_FCSR; + } + write_smstateen(env, reg, wr_mask, val); return RISCV_EXCP_NONE; @@ -2048,6 +2060,10 @@ static RISCVException write_hstateen(CPURISCVState *env, int csrno, uint64_t wr_mask = 1UL << SMSTATEEN_STATEN; int index = csrno - CSR_HSTATEEN0; + if (riscv_has_ext(env, RVF)) { + wr_mask |= 1UL << SMSTATEEN0_FCSR; + } + reg = &env->hstateen[index]; wr_mask &= env->mstateen[index]; write_smstateen(env, reg, wr_mask, new_val); @@ -2071,6 +2087,10 @@ static RISCVException write_hstateenh(CPURISCVState *env, int csrno, uint64_t wr_mask = 1UL << SMSTATEEN_STATEN; int index = csrno - CSR_HSTATEEN0H - 0x10; + if (riscv_has_ext(env, RVF)) { + wr_mask |= 1UL << SMSTATEEN0_FCSR; + } + reg = &env->hstateen[index]; val = (uint64_t)new_val << 32; val |= *reg & 0xFFFFFFFF; @@ -2096,6 +2116,10 @@ static RISCVException write_sstateen(CPURISCVState *env, int csrno, int index = csrno - CSR_SSTATEEN0; bool virt = riscv_cpu_virt_enabled(env); + if (riscv_has_ext(env, RVF)) { + wr_mask |= 1UL << SMSTATEEN0_FCSR; + } + reg = &env->sstateen[index]; if (virt) { wr_mask &= env->mstateen[index]; -- 2.17.1