Re: [PATCH 03/12] PCI: dwc: Add unroll iATU space support to the regions disable method

[Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>]

On Thu, Mar 24, 2022 at 04:25:14AM +0300, Serge Semin wrote:
> The dw_pcie_disable_atu() method was introduced in the commit f8aed6ec624f
> ("PCI: dwc: designware: Add EP mode support"). Since then it hasn't
> changed at all.  For all that time the method has supported the viewport
> version of the iATU CSRs only. Basically it works for the DW PCIe IP-cores
> older than v4.80a since the newer controllers are equipped with the
> unrolled iATU/eDMA space. It means the methods using it like
> pci_epc_ops.clear_bar and pci_epc_ops.unmap_addr callbacks just don't work
> correctly for the DW PCIe controllers with unrolled iATU CSRs. The same
> concerns the dw_pcie_setup_rc() method, which disables the outbound iATU
> entries before re-initializing them.
> 
> So in order to fix the problems denoted above let's convert the
> dw_pcie_disable_atu() method to disabling the iATU inbound and outbound
> regions in the unrolled iATU CSRs in case the DW PCIe controller has been
> synthesized with the ones support. The former semantics will be remained
> for the controller having iATU mapped over the viewport.
> 
> Fixes: f8aed6ec624f ("PCI: dwc: designware: Add EP mode support")
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  drivers/pci/controller/dwc/pcie-designware.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index d92c8a25094f..7dc8c360a0d4 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -504,8 +504,18 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
>  		return;
>  	}
>  
> -	dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
> -	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE);
> +	if (pci->iatu_unroll_enabled) {
> +		if (region == PCIE_ATU_REGION_INBOUND) {
> +			dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
> +						 ~(u32)PCIE_ATU_ENABLE);
> +		} else {
> +			dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
> +						 ~(u32)PCIE_ATU_ENABLE);
> +		}
> +	} else {
> +		dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
> +		dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE);
> +	}
>  }
>  
>  int dw_pcie_wait_for_link(struct dw_pcie *pci)
> -- 
> 2.35.1
>