From: Christoph Hellwig <hch@lst.de>
To: Heiko Stuebner <heiko@sntech.de>
Cc: palmer@dabbelt.com, paul.walmsley@sifive.com,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
wefu@redhat.com, guoren@kernel.org, atishp@atishpatra.org,
anup@brainfault.org, mick@ics.forth.gr, samuel@sholland.org,
cmuellner@linux.com, philipp.tomsich@vrull.eu,
Christoph Hellwig <hch@lst.de>, Atish Patra <atish.patra@wdc.com>
Subject: Re: [PATCH 1/2] riscv: Implement Zicbom-based cache management operations
Date: Thu, 31 Mar 2022 12:07:01 +0200 [thread overview]
Message-ID: <20220331100701.GJ23422@lst.de> (raw)
In-Reply-To: <20220307224620.1933061-2-heiko@sntech.de>
I somehow only got patch 1 out of 2, which makes reviewing this very
hard.
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WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: Heiko Stuebner <heiko@sntech.de>
Cc: palmer@dabbelt.com, paul.walmsley@sifive.com,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
wefu@redhat.com, guoren@kernel.org, atishp@atishpatra.org,
anup@brainfault.org, mick@ics.forth.gr, samuel@sholland.org,
cmuellner@linux.com, philipp.tomsich@vrull.eu,
Christoph Hellwig <hch@lst.de>, Atish Patra <atish.patra@wdc.com>
Subject: Re: [PATCH 1/2] riscv: Implement Zicbom-based cache management operations
Date: Thu, 31 Mar 2022 12:07:01 +0200 [thread overview]
Message-ID: <20220331100701.GJ23422@lst.de> (raw)
In-Reply-To: <20220307224620.1933061-2-heiko@sntech.de>
I somehow only got patch 1 out of 2, which makes reviewing this very
hard.
next prev parent reply other threads:[~2022-03-31 10:07 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-07 22:46 [PATCH 0/2] riscv: implement Zicbom-based CMO instructions + the t-head variant Heiko Stuebner
2022-03-07 22:46 ` Heiko Stuebner
2022-03-07 22:46 ` [PATCH 1/2] riscv: Implement Zicbom-based cache management operations Heiko Stuebner
2022-03-07 22:46 ` Heiko Stuebner
2022-03-25 16:20 ` Anup Patel
2022-03-25 16:20 ` Anup Patel
2022-03-25 17:24 ` Philipp Tomsich
2022-03-25 17:24 ` Philipp Tomsich
[not found] ` <CAAeLtUAi+61Hk7oBW979QEKYaume3vqdt_KkS_mXpRAs+CzHnA@mail.gmail.com>
2022-03-25 17:37 ` Anup Patel
2022-03-25 17:37 ` Anup Patel
2022-03-31 10:07 ` Christoph Hellwig [this message]
2022-03-31 10:07 ` Christoph Hellwig
2022-03-07 22:46 ` [PATCH 2/2] riscv: implement cache-management errata for T-Head SoCs Heiko Stuebner
2022-03-07 22:46 ` Heiko Stuebner
2022-03-31 2:30 ` Palmer Dabbelt
2022-03-31 2:30 ` Palmer Dabbelt
2022-03-31 8:22 ` Heiko Stübner
2022-03-31 8:22 ` Heiko Stübner
2022-03-31 8:29 ` Philipp Tomsich
2022-03-31 8:29 ` Philipp Tomsich
2022-04-20 0:18 ` Palmer Dabbelt
2022-04-20 0:18 ` Palmer Dabbelt
2022-04-01 1:05 ` Samuel Holland
2022-04-01 1:05 ` Samuel Holland
2022-04-15 11:26 ` [PATCH 0/2] riscv: implement Zicbom-based CMO instructions + the t-head variant Corentin Labbe
2022-04-15 11:26 ` Corentin Labbe
2022-04-16 2:19 ` Samuel Holland
2022-04-16 2:19 ` Samuel Holland
2022-04-16 7:35 ` Corentin Labbe
2022-04-16 7:35 ` Corentin Labbe
2022-04-16 17:47 ` Samuel Holland
2022-04-16 17:47 ` Samuel Holland
2022-04-16 19:32 ` Corentin Labbe
2022-04-16 19:32 ` Corentin Labbe
2022-04-17 2:17 ` Guo Ren
2022-04-17 2:17 ` Guo Ren
2022-04-17 8:45 ` Corentin Labbe
2022-04-17 8:45 ` Corentin Labbe
2022-04-17 8:49 ` Guo Ren
2022-04-17 8:49 ` Guo Ren
2022-04-17 17:35 ` Corentin Labbe
2022-04-17 17:35 ` Corentin Labbe
2022-04-17 22:50 ` Guo Ren
2022-04-17 22:50 ` Guo Ren
2022-04-19 7:44 ` Corentin Labbe
2022-04-19 7:44 ` Corentin Labbe
2022-04-18 15:29 ` Philipp Tomsich
2022-04-18 15:29 ` Philipp Tomsich
2022-04-19 7:52 ` Corentin Labbe
2022-04-19 7:52 ` Corentin Labbe
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