From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EAE9C4167B for ; Mon, 4 Apr 2022 21:27:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379702AbiDDV2k (ORCPT ); Mon, 4 Apr 2022 17:28:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1381018AbiDDVWU (ORCPT ); Mon, 4 Apr 2022 17:22:20 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9C981D30D for ; Mon, 4 Apr 2022 14:20:10 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id h16-20020a056902009000b00628a70584b2so8763399ybs.6 for ; Mon, 04 Apr 2022 14:20:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:message-id:mime-version:subject:from:to:cc; bh=DBbP7cPmiHpe5TN1/LJtSaqk7J0plWu8gjlZ5CS5rhk=; b=TZ0NkmLInAy4kYp/+n01zKn7zzlAQwYbOYU6jY1KwnR3G5n4mVA4WMp89xHymMNtfP 0tsioSzKKpVGh67W/c1oyCZw3dCUqaR2fQfw96LIJgjhSjM95BmdvEizNAM9WtPEkVRr DtPgeu6pBu0zAl/vnsNkAlAedpxW1AbHCIIlZNKZ5PhYuY4Jiq195R0OGaA2XuKtrUMO qnziyHF0S9GwK33CJbi7GF24qNjf1bt3oMgloRa3IvwBBBe70DLX2iqKTlCePVN/MzQT 72VosHjFPeonT+rgF2nwR4hz9j+vV4BAGXKPlqp54r6c2l1MfTmTcFNXu2qmhZxWkFUO UFaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=DBbP7cPmiHpe5TN1/LJtSaqk7J0plWu8gjlZ5CS5rhk=; b=BdttMWXHLaarvGPWsQ3Vz+RwIWqWmAU46u440OLFtGih/sOteAQjldi2RfEdB3n654 yxiujr1GAy5elXnPvif/vhHt7ha51D4y+vidRy1wcCWOtI+f93cHbuNlPJsftwAOnVz1 RtY7WuRU9Bva9q3t0WObKCOXLbeqC7MCVOaecVFETbQYjvk/Ie+qdeWk/3aQ6JL2JmJk ROkHkF4YDYIC+mD8hC5huw7pN9IjeJLOmiwcTvbrKbenPClKoLgwO6y80N87jQwBpegj 1qX+KSlxE0qY98Z2o1DA1G/I4dfcZZix98fCF6yprgD2LSeOheTlwKd/phzE1Flq0i48 Uj1g== X-Gm-Message-State: AOAM530F9NC0zW0cyAeA47F1wFIyNTjIlNfUsm53fcVHGLdzZzTcmP/j 122R0DD0WSuU1Ig5Hk0Ddx9iYaY= X-Google-Smtp-Source: ABdhPJwynxzOo1uDL3PwMweufxLtr415yHT/T9PLgILZC1tllY8xKXYrs4PdKMB9UD3Be3KOTlIn+Bs= X-Received: from pcc-desktop.svl.corp.google.com ([2620:15c:2ce:200:e34c:522f:9edd:2978]) (user=pcc job=sendgmr) by 2002:a05:690c:13:b0:2dc:50bc:c975 with SMTP id bc19-20020a05690c001300b002dc50bcc975mr17931ywb.173.1649107144995; Mon, 04 Apr 2022 14:19:04 -0700 (PDT) Date: Mon, 4 Apr 2022 14:18:58 -0700 Message-Id: <20220404211858.968452-1-pcc@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.35.1.1094.g7c7d902a7c-goog Subject: [PATCH] arm64: document the boot requirements for MTE From: Peter Collingbourne To: Catalin Marinas , Will Deacon , Jonathan Corbet , Mark Brown Cc: Peter Collingbourne , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org When booting the kernel we access system registers such as GCR_EL1 if MTE is supported. These accesses are defined to trap to EL3 if SCR_EL3.ATA is disabled. Furthermore, tag accesses will not behave as expected if SCR_EL3.ATA is not set, or if HCR_EL2.ATA is not set and we were booted at EL1. Therefore, require that these bits are enabled when appropriate. Signed-off-by: Peter Collingbourne Link: https://linux-review.googlesource.com/id/Iadcfd4dcd9ba3279b2813970b44d7485b0116709 --- Documentation/arm64/booting.rst | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index 29884b261aa9..833af981b667 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -350,6 +350,16 @@ Before jumping into the kernel, the following conditions must be met: - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1. + For CPUs with the Memory Tagging Extension feature: + + - If EL3 is present: + + - SCR_EL3.ATA (bit 26) must be initialised to 0b1. + + - If the kernel is entered at EL1 and EL2 is present: + + - HCR_EL2.ATA (bit 56) must be initialised to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. Where the values documented -- 2.35.1.1094.g7c7d902a7c-goog From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B6CAEC433EF for ; Mon, 4 Apr 2022 21:20:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Mime-Version: Message-Id:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=Yuk6be8uZ9I5kqgQ+LtGotxVC58Lxg9XQtklPE52QQ8=; b=eIG DNQTg2pteUzslhCx2lwwYswI7aS+iWYdvmDkuwxilxBOh5E2GG5b9mylqfZcYbGHiACtHObPnA5oe pI6EBtOe2Gxtmw4wAp3/1UdBgeFyK9g+jIZ2HHygIbkxXZBfUBzV2vdYgAIgh2kelX11mo+KprgI7 Bl1a4hp8+w/T6rqBAX5/sQO/wlOiLnRP2b9eC5Y91k7tiE1zv6mpalVZ6az/sysF21lQneuaCtZ+F Nnqpt6G2TEjm6wP5MWV90d5fwzA+CV39eHchbJtmSRRTIsJPBI0cRqQ2l7xHaTMw8O7oZy3uks9qQ hoq9VJCoigJeOsGPfPDm5m3hRxFHK/Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nbU6S-00GQxX-TU; Mon, 04 Apr 2022 21:19:13 +0000 Received: from mail-yw1-x1149.google.com ([2607:f8b0:4864:20::1149]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nbU6P-00GQwA-2G for linux-arm-kernel@lists.infradead.org; Mon, 04 Apr 2022 21:19:10 +0000 Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-2e9eb7d669fso92030957b3.14 for ; Mon, 04 Apr 2022 14:19:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:message-id:mime-version:subject:from:to:cc; bh=DBbP7cPmiHpe5TN1/LJtSaqk7J0plWu8gjlZ5CS5rhk=; b=TZ0NkmLInAy4kYp/+n01zKn7zzlAQwYbOYU6jY1KwnR3G5n4mVA4WMp89xHymMNtfP 0tsioSzKKpVGh67W/c1oyCZw3dCUqaR2fQfw96LIJgjhSjM95BmdvEizNAM9WtPEkVRr DtPgeu6pBu0zAl/vnsNkAlAedpxW1AbHCIIlZNKZ5PhYuY4Jiq195R0OGaA2XuKtrUMO qnziyHF0S9GwK33CJbi7GF24qNjf1bt3oMgloRa3IvwBBBe70DLX2iqKTlCePVN/MzQT 72VosHjFPeonT+rgF2nwR4hz9j+vV4BAGXKPlqp54r6c2l1MfTmTcFNXu2qmhZxWkFUO UFaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=DBbP7cPmiHpe5TN1/LJtSaqk7J0plWu8gjlZ5CS5rhk=; b=bSLLz4N+E6cwQzF9wZOCWYbvFvC7fdFAAuTZHC0/ygMpg9L5pFOGeLloXuTdXgpV+K xxr4K//+Vftne7Pd8Y3Wt7tdSprNlNsrJ9eSZR4q2odwfcMIlJqVv3zaTVZR8iNjYAlC kd49qX/4Jn0Kyw5VaaezDfm8zYCuUSTaUbhN/lw2gG+jBEa1s/P0RPnaRRKnXhHdxJdo VBBzfHhTwWjsq4xjR38gG+n/IFcbMtTGVrcy7axgOCzb94ZT75bGAZEltMQTPkWfY++N 8LAGZMQXPul+Vq8YiIIJWi5MYkyQWa5auFT70ifuUBUAyxKEVm4wnF7jPe5eIdGhl80I SYLw== X-Gm-Message-State: AOAM5309MLI747W/g+ntz8xDCQxjiD2nvLBtPjHKCN6A9iMy3s/StEzC Ab+1SPrW9hAUNum432o6lr/XRnM= X-Google-Smtp-Source: ABdhPJwynxzOo1uDL3PwMweufxLtr415yHT/T9PLgILZC1tllY8xKXYrs4PdKMB9UD3Be3KOTlIn+Bs= X-Received: from pcc-desktop.svl.corp.google.com ([2620:15c:2ce:200:e34c:522f:9edd:2978]) (user=pcc job=sendgmr) by 2002:a05:690c:13:b0:2dc:50bc:c975 with SMTP id bc19-20020a05690c001300b002dc50bcc975mr17931ywb.173.1649107144995; Mon, 04 Apr 2022 14:19:04 -0700 (PDT) Date: Mon, 4 Apr 2022 14:18:58 -0700 Message-Id: <20220404211858.968452-1-pcc@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.35.1.1094.g7c7d902a7c-goog Subject: [PATCH] arm64: document the boot requirements for MTE From: Peter Collingbourne To: Catalin Marinas , Will Deacon , Jonathan Corbet , Mark Brown Cc: Peter Collingbourne , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220404_141909_140747_1BD64EAB X-CRM114-Status: GOOD ( 12.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When booting the kernel we access system registers such as GCR_EL1 if MTE is supported. These accesses are defined to trap to EL3 if SCR_EL3.ATA is disabled. Furthermore, tag accesses will not behave as expected if SCR_EL3.ATA is not set, or if HCR_EL2.ATA is not set and we were booted at EL1. Therefore, require that these bits are enabled when appropriate. Signed-off-by: Peter Collingbourne Link: https://linux-review.googlesource.com/id/Iadcfd4dcd9ba3279b2813970b44d7485b0116709 --- Documentation/arm64/booting.rst | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index 29884b261aa9..833af981b667 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -350,6 +350,16 @@ Before jumping into the kernel, the following conditions must be met: - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1. + For CPUs with the Memory Tagging Extension feature: + + - If EL3 is present: + + - SCR_EL3.ATA (bit 26) must be initialised to 0b1. + + - If the kernel is entered at EL1 and EL2 is present: + + - HCR_EL2.ATA (bit 56) must be initialised to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. Where the values documented -- 2.35.1.1094.g7c7d902a7c-goog _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel