From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9ABDC433F5 for ; Fri, 8 Apr 2022 03:34:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231473AbiDHDgE (ORCPT ); Thu, 7 Apr 2022 23:36:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230133AbiDHDgD (ORCPT ); Thu, 7 Apr 2022 23:36:03 -0400 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FBB41D2B47; Thu, 7 Apr 2022 20:34:00 -0700 (PDT) Received: by mail-pg1-x531.google.com with SMTP id q142so6658799pgq.9; Thu, 07 Apr 2022 20:34:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to; bh=dw+ROn8RvBkqEEh4rGoMJ1WVteSRDkuc1/T16Z5qZMc=; b=EeBrjzYK8SkX1OqjP+i4bvgZKa+egv6bbbX6Xseqd75gu8/cTyTmEKI66pcq42X4Tt jUu+tdejhl+pgRUDFf3ekJue/654i8tzbQvbIqOElao4jnOElmCskBymalqtkaTdS7td 4B41UNZxOQSsBUXzZI7JAuypNaXHFhb90Int7OPOhfDVDz7wMoiEOiUf8ka6R2+Qk7H0 2SHBCSD0e181CRTA+6Ww96XYGQD6xsDEiQ/BlD4kvrq4ITL/TcB1KFDGKNft7l/ycYcC l666RQJjkeA7+bKN3J4WOGxeH8isiZMHyGn8NoU+Am/JyeLwRLmzOppBIF6BOofCi9mi IqdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=dw+ROn8RvBkqEEh4rGoMJ1WVteSRDkuc1/T16Z5qZMc=; b=mJF17z/z7me98J0N1Piupk6WPYhieZxg7exRZwf8Y1nT5jcHiBPslDK3t7L3gBZRlv g4mLYYKm9XNh4TF4mxtn4TPEr1tYL0kMv9Nf3TnewmqOhRME5ArucHNXJkONCtdzn80Z HT50FuVZXOrT2RwBRBWWrhXNcc6vviRa0aLFYGxM9LCMDrXizj5fkGMijBwSgxU0r27H yoQfgXfZb/UE9hi/0RxB7/eiXuD4MBvfM/+kzMg3mZwHhiH74dZSqNusupijoMTY/hT1 3zCHgGwXBhs2L8LQ/y/HKxYPOT9SOq+gZW3YRaLfZJRI/RQaSFPBVnAMphfyBDhZPqAF YBfw== X-Gm-Message-State: AOAM531Y/eV58Ja8e7DILfILX1GTcKqETKxfheeq0yqXMQaOA2V32EC5 jC2Jfmior7DPo2sA7iMuQjk= X-Google-Smtp-Source: ABdhPJw2JVZSjgvThPvGb8qxgxHfxjyJ37Kl9thDcERfEhZZSRsH+ojMV4RqYMA6JgZqguQ1nXD3wg== X-Received: by 2002:a63:f24c:0:b0:383:c279:e662 with SMTP id d12-20020a63f24c000000b00383c279e662mr13907253pgk.303.1649388839948; Thu, 07 Apr 2022 20:33:59 -0700 (PDT) Received: from localhost ([192.55.54.52]) by smtp.gmail.com with ESMTPSA id r10-20020a17090a454a00b001c96a912aa0sm10618624pjm.3.2022.04.07.20.33.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Apr 2022 20:33:59 -0700 (PDT) Date: Thu, 7 Apr 2022 20:33:57 -0700 From: Isaku Yamahata To: Kai Huang Cc: Xiaoyao Li , Paolo Bonzini , isaku.yamahata@intel.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, isaku.yamahata@gmail.com, Jim Mattson , erdemaktas@google.com, Connor Kuehl , Sean Christopherson Subject: Re: [RFC PATCH v5 027/104] KVM: TDX: initialize VM with TDX specific parameters Message-ID: <20220408033357.GF2864606@ls.amr.corp.intel.com> References: <34d773c8d32c8d38033aae7e0fee572d757e242c.camel@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <34d773c8d32c8d38033aae7e0fee572d757e242c.camel@intel.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Thu, Apr 07, 2022 at 01:51:38PM +1200, Kai Huang wrote: > On Thu, 2022-04-07 at 09:29 +0800, Xiaoyao Li wrote: > > On 4/5/2022 8:58 PM, Paolo Bonzini wrote: > > > On 3/4/22 20:48, isaku.yamahata@intel.com wrote: > > > > +    td_params->attributes = init_vm->attributes; > > > > +    if (td_params->attributes & TDX_TD_ATTRIBUTE_PERFMON) { > > > > +        pr_warn("TD doesn't support perfmon. KVM needs to save/restore " > > > > +            "host perf registers properly.\n"); > > > > +        return -EOPNOTSUPP; > > > > +    } > > > > > > Why does KVM have to hardcode this (and LBR/AMX below)?  Is the level of > > > hardware support available from tdx_caps, for example through the CPUID > > > configs (0xA for this one, 0xD for LBR and AMX)? > > > > It's wrong code. PMU is allowed. > > > > AMX and LBR are disallowed because and the time we wrote the codes they > > are not supported by KVM. Now AMX should be allowed, but (arch-)LBR > > should be still blocked until KVM merges arch-LBR support. > > I think Isaku's idea is we don't support them in the first submission? > > If so as I suggested, we should add a TODO in comment.. Sure, will add a TODO comment. -- Isaku Yamahata