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[31.208.27.151]) by smtp.gmail.com with ESMTPSA id f2-20020a2eb5a2000000b0024b52055ce1sm1081920ljn.104.2022.04.11.15.16.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 15:16:03 -0700 (PDT) Date: Tue, 12 Apr 2022 00:16:02 +0200 From: Francisco Iglesias To: "Michael S. Tsirkin" Subject: Re: [RFC PATCH v1 1/1] include/hw/pci/pcie_host: Correct PCIE_MMCFG_BUS_MASK Message-ID: <20220411221601.GA17303@fralle-msi> References: <20220411193818.8845-1-frasse.iglesias@gmail.com> <20220411171149-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220411171149-mutt-send-email-mst@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=frasse.iglesias@gmail.com; helo=mail-lf1-x133.google.com X-Spam_score_int: -1020 X-Spam_score: -102.1 X-Spam_bar: --------------------------------------------------- X-Spam_report: (-102.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_WELCOMELIST=-0.01, USER_IN_WHITELIST=-100 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Michael, On [2022 Apr 11] Mon 17:12:47, Michael S. Tsirkin wrote: > On Mon, Apr 11, 2022 at 09:38:18PM +0200, Francisco Iglesias wrote: > > According to [1] address bits 27 - 20 are mapped to the bus number (the > > TLPs bus number field is 8 bits). > > > > [1] PCI Express® Base Specification Revision 5.0 Version 1.0 > > > > Signed-off-by: Francisco Iglesias > > --- > > include/hw/pci/pcie_host.h | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h > > index 076457b270..b3c8ce973c 100644 > > --- a/include/hw/pci/pcie_host.h > > +++ b/include/hw/pci/pcie_host.h > > @@ -60,7 +60,7 @@ void pcie_host_mmcfg_update(PCIExpressHost *e, > > /* > > * PCI express ECAM (Enhanced Configuration Address Mapping) format. > > * AKA mmcfg address > > - * bit 20 - 28: bus number > > + * bit 20 - 27: bus number > > * bit 15 - 19: device number > > * bit 12 - 14: function number > > * bit 0 - 11: offset in configuration space of a given device > > this is correct, or to be more precise: > A[(20 + n – 1):20] and 1 <= n <= 8 Thank you for having a look! I'll create a patch for this and also a second proposing a correction for PCIE_MMCFG_SIZE_MAX and repost! Best regards, Francisco > > > > @@ -68,7 +68,7 @@ void pcie_host_mmcfg_update(PCIExpressHost *e, > > #define PCIE_MMCFG_SIZE_MAX (1ULL << 29) > > #define PCIE_MMCFG_SIZE_MIN (1ULL << 20) > > #define PCIE_MMCFG_BUS_BIT 20 > > -#define PCIE_MMCFG_BUS_MASK 0x1ff > > +#define PCIE_MMCFG_BUS_MASK 0xff > > #define PCIE_MMCFG_DEVFN_BIT 12 > > #define PCIE_MMCFG_DEVFN_MASK 0xff > > #define PCIE_MMCFG_CONFOFFSET_MASK 0xfff > > -- > > 2.20.1 >