Re: [PATCH v4 4/4] PCI: mvebu: Add support for sending Set_Slot_Power_Limit message

[kernel test robot <lkp@intel.com>]

Hi "Pali,

I love your patch! Yet something to improve:

[auto build test ERROR on helgaas-pci/next]
[also build test ERROR on robh/for-next v5.18-rc2 next-20220411]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/intel-lab-lkp/linux/commits/Pali-Roh-r/PCI-mvebu-Slot-support/20220412-030318
base:   https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: arm-dove_defconfig (https://download.01.org/0day-ci/archive/20220412/202204121218.2C0C4sRc-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project c6e83f560f06cdfe8aa47b248d8bdc58f947274b)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm cross compiling tool for clang build
        # apt-get install binutils-arm-linux-gnueabi
        # https://github.com/intel-lab-lkp/linux/commit/5453bfff3f906999c849d3e495990951fbe59fc9
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Pali-Roh-r/PCI-mvebu-Slot-support/20220412-030318
        git checkout 5453bfff3f906999c849d3e495990951fbe59fc9
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> drivers/pci/controller/pci-mvebu.c:663:11: error: use of undeclared identifier 'slotctl'; did you mean 'slotsta'?
                           val |= slotctl & PCI_EXP_SLTCTL_ASPL_DISABLE;
                                  ^~~~~~~
                                  slotsta
   drivers/pci/controller/pci-mvebu.c:655:7: note: 'slotsta' declared here
                   u16 slotsta = le16_to_cpu(bridge->pcie_conf.slotsta);
                       ^
   1 error generated.


vim +663 drivers/pci/controller/pci-mvebu.c

   620	
   621	static pci_bridge_emul_read_status_t
   622	mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
   623					     int reg, u32 *value)
   624	{
   625		struct mvebu_pcie_port *port = bridge->data;
   626	
   627		switch (reg) {
   628		case PCI_EXP_DEVCAP:
   629			*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP);
   630			break;
   631	
   632		case PCI_EXP_DEVCTL:
   633			*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
   634			break;
   635	
   636		case PCI_EXP_LNKCAP:
   637			/*
   638			 * PCIe requires that the Clock Power Management capability bit
   639			 * is hard-wired to zero for downstream ports but HW returns 1.
   640			 * Additionally enable Data Link Layer Link Active Reporting
   641			 * Capable bit as DL_Active indication is provided too.
   642			 */
   643			*value = (mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) &
   644				  ~PCI_EXP_LNKCAP_CLKPM) | PCI_EXP_LNKCAP_DLLLARC;
   645			break;
   646	
   647		case PCI_EXP_LNKCTL:
   648			/* DL_Active indication is provided via PCIE_STAT_OFF */
   649			*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL) |
   650				 (mvebu_pcie_link_up(port) ?
   651				  (PCI_EXP_LNKSTA_DLLLA << 16) : 0);
   652			break;
   653	
   654		case PCI_EXP_SLTCTL: {
   655			u16 slotsta = le16_to_cpu(bridge->pcie_conf.slotsta);
   656			u32 val = 0;
   657			/*
   658			 * When slot power limit was not specified in DT then
   659			 * ASPL_DISABLE bit is stored only in emulated config space.
   660			 * Otherwise reflect status of PCIE_SSPL_ENABLE bit in HW.
   661			 */
   662			if (!port->slot_power_limit_value)
 > 663				val |= slotctl & PCI_EXP_SLTCTL_ASPL_DISABLE;
   664			else if (!(mvebu_readl(port, PCIE_SSPL_OFF) & PCIE_SSPL_ENABLE))
   665				val |= PCI_EXP_SLTCTL_ASPL_DISABLE;
   666			/* This callback is 32-bit and in high bits is slot status. */
   667			val |= slotsta << 16;
   668			*value = val;
   669			break;
   670		}
   671	
   672		case PCI_EXP_RTSTA:
   673			*value = mvebu_readl(port, PCIE_RC_RTSTA);
   674			break;
   675	
   676		case PCI_EXP_DEVCAP2:
   677			*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP2);
   678			break;
   679	
   680		case PCI_EXP_DEVCTL2:
   681			*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL2);
   682			break;
   683	
   684		case PCI_EXP_LNKCTL2:
   685			*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL2);
   686			break;
   687	
   688		default:
   689			return PCI_BRIDGE_EMUL_NOT_HANDLED;
   690		}
   691	
   692		return PCI_BRIDGE_EMUL_HANDLED;
   693	}
   694	

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