CXL type 3 which doesn't have cxl mem enabled.

[Jonathan Cameron <Jonathan.Cameron@Huawei.com>]

Hi All,

I ran into this whilst debugging why on the current QEMU code
we now get a probe failure for CXL mem due to the range 1 size being
non 0. 

The conditions for whether we have legacy ranges programmed don't
take into account if Mem_Enable = 1.  That is if the
DVSEC CXL Control Mem_Enable bit is set on the type 3 device.
If it's not then there is no existing user of the CXL memory
setup by firmware or similar so we can switch over to HDM
decoders and it doesn't matter what is in the range registers.

Unfortunately the QEMU code was bringing the device up with
Mem_Enabled already set.  So I fixed that.  After all default
value of that bit should be 0.

A few problems then showed up.

1. Nothing in the Linux code actually sets Mem_Enabled to 1.
2. Probing fails in mem.c as wait_for_media() checks for
   info->mem_enabled (cached value of this bit).

So, dirty hack was to 
* drop that check in wait_for_media() as media being enabled doesn't
  have much to do with CXL.mem protocol being enabled.
* Make the check in cxl_hdm_decode_init()
   if (info->mem_enabled && !global_enable && info->ranges)
* Immediately after enabling the hdm decoder global enable,
  also set the Mem_Enable bit also update info->mem_enabled.

This seems to work, but I can't help thinking I'm missing something.

Jonathan