From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com,
peter.maydell@linaro.org, richard.henderson@linaro.org,
"Víctor Colombo" <victor.colombo@eldorado.org.br>
Subject: [PULL 09/30] target/ppc: Remove fpscr_* macros from cpu.h
Date: Thu, 5 May 2022 15:49:17 -0300 [thread overview]
Message-ID: <20220505184938.351866-10-danielhb413@gmail.com> (raw)
In-Reply-To: <20220505184938.351866-1-danielhb413@gmail.com>
From: Víctor Colombo <victor.colombo@eldorado.org.br>
fpscr_* defined macros are hiding the usage of *env behind them.
Substitute the usage of these macros with `env->fpscr & FP_*` to make
the code cleaner.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Message-Id: <20220504210541.115256-2-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/cpu.c | 2 +-
target/ppc/cpu.h | 29 -----------------------------
target/ppc/fpu_helper.c | 28 ++++++++++++++--------------
3 files changed, 15 insertions(+), 44 deletions(-)
diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index d7b42bae52..401b6f9e63 100644
--- a/target/ppc/cpu.c
+++ b/target/ppc/cpu.c
@@ -88,7 +88,7 @@ static inline void fpscr_set_rounding_mode(CPUPPCState *env)
int rnd_type;
/* Set rounding mode */
- switch (fpscr_rn) {
+ switch (env->fpscr & FP_RN) {
case 0:
/* Best approximation (round to nearest) */
rnd_type = float_round_nearest_even;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index c2b6c987c0..ad31e51d69 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -713,41 +713,12 @@ enum {
#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
#define FPSCR_RN1 1
#define FPSCR_RN0 0 /* Floating-point rounding control */
-#define fpscr_drn (((env->fpscr) & FP_DRN) >> FPSCR_DRN0)
-#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
-#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
-#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
-#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
-#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
-#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
-#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
-#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
-#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
-#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
-#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
-#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
-#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
-#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
-#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
-#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
-#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
-#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
-#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
-#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
-#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
-#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
-#define fpscr_rn (((env->fpscr) >> FPSCR_RN0) & 0x3)
/* Invalid operation exception summary */
#define FPSCR_IX ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
(1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
(1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
(1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
(1 << FPSCR_VXCVI))
-/* exception summary */
-#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
-/* enabled exception summary */
-#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
- 0x1F)
#define FP_DRN2 (1ull << FPSCR_DRN2)
#define FP_DRN1 (1ull << FPSCR_DRN1)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 99281cc37a..f6c8318a71 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -202,7 +202,7 @@ static void finish_invalid_op_excp(CPUPPCState *env, int op, uintptr_t retaddr)
env->fpscr |= FP_VX;
/* Update the floating-point exception summary */
env->fpscr |= FP_FX;
- if (fpscr_ve != 0) {
+ if (env->fpscr & FP_VE) {
/* Update the floating-point enabled exception summary */
env->fpscr |= FP_FEX;
if (fp_exceptions_enabled(env)) {
@@ -216,7 +216,7 @@ static void finish_invalid_op_arith(CPUPPCState *env, int op,
bool set_fpcc, uintptr_t retaddr)
{
env->fpscr &= ~(FP_FR | FP_FI);
- if (fpscr_ve == 0) {
+ if (!(env->fpscr & FP_VE)) {
if (set_fpcc) {
env->fpscr &= ~FP_FPCC;
env->fpscr |= (FP_C | FP_FU);
@@ -286,7 +286,7 @@ static void float_invalid_op_vxvc(CPUPPCState *env, bool set_fpcc,
/* Update the floating-point exception summary */
env->fpscr |= FP_FX;
/* We must update the target FPR before raising the exception */
- if (fpscr_ve != 0) {
+ if (env->fpscr & FP_VE) {
CPUState *cs = env_cpu(env);
cs->exception_index = POWERPC_EXCP_PROGRAM;
@@ -303,7 +303,7 @@ static void float_invalid_op_vxcvi(CPUPPCState *env, bool set_fpcc,
{
env->fpscr |= FP_VXCVI;
env->fpscr &= ~(FP_FR | FP_FI);
- if (fpscr_ve == 0) {
+ if (!(env->fpscr & FP_VE)) {
if (set_fpcc) {
env->fpscr &= ~FP_FPCC;
env->fpscr |= (FP_C | FP_FU);
@@ -318,7 +318,7 @@ static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr)
env->fpscr &= ~(FP_FR | FP_FI);
/* Update the floating-point exception summary */
env->fpscr |= FP_FX;
- if (fpscr_ze != 0) {
+ if (env->fpscr & FP_ZE) {
/* Update the floating-point enabled exception summary */
env->fpscr |= FP_FEX;
if (fp_exceptions_enabled(env)) {
@@ -336,7 +336,7 @@ static inline void float_overflow_excp(CPUPPCState *env)
env->fpscr |= FP_OX;
/* Update the floating-point exception summary */
env->fpscr |= FP_FX;
- if (fpscr_oe != 0) {
+ if (env->fpscr & FP_OE) {
/* XXX: should adjust the result */
/* Update the floating-point enabled exception summary */
env->fpscr |= FP_FEX;
@@ -356,7 +356,7 @@ static inline void float_underflow_excp(CPUPPCState *env)
env->fpscr |= FP_UX;
/* Update the floating-point exception summary */
env->fpscr |= FP_FX;
- if (fpscr_ue != 0) {
+ if (env->fpscr & FP_UE) {
/* XXX: should adjust the result */
/* Update the floating-point enabled exception summary */
env->fpscr |= FP_FEX;
@@ -374,7 +374,7 @@ static inline void float_inexact_excp(CPUPPCState *env)
env->fpscr |= FP_XX;
/* Update the floating-point exception summary */
env->fpscr |= FP_FX;
- if (fpscr_xe != 0) {
+ if (env->fpscr & FP_XE) {
/* Update the floating-point enabled exception summary */
env->fpscr |= FP_FEX;
/* We must update the target FPR before raising the exception */
@@ -2274,7 +2274,7 @@ VSX_MADDQ(XSNMSUBQPO, NMSUB_FLGS, 0)
vxvc = svxvc; \
if (flags & float_flag_invalid_snan) { \
float_invalid_op_vxsnan(env, GETPC()); \
- vxvc &= fpscr_ve == 0; \
+ vxvc &= !(env->fpscr & FP_VE); \
} \
if (vxvc) { \
float_invalid_op_vxvc(env, 0, GETPC()); \
@@ -2375,7 +2375,7 @@ static inline void do_scalar_cmp(CPUPPCState *env, ppc_vsr_t *xa, ppc_vsr_t *xb,
if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) ||
float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) {
vxsnan_flag = true;
- if (fpscr_ve == 0 && ordered) {
+ if (!(env->fpscr & FP_VE) && ordered) {
vxvc_flag = true;
}
} else if (float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) ||
@@ -2440,7 +2440,7 @@ static inline void do_scalar_cmpq(CPUPPCState *env, ppc_vsr_t *xa,
if (float128_is_signaling_nan(xa->f128, &env->fp_status) ||
float128_is_signaling_nan(xb->f128, &env->fp_status)) {
vxsnan_flag = true;
- if (fpscr_ve == 0 && ordered) {
+ if (!(env->fpscr & FP_VE) && ordered) {
vxvc_flag = true;
}
} else if (float128_is_quiet_nan(xa->f128, &env->fp_status) ||
@@ -2590,7 +2590,7 @@ void helper_##name(CPUPPCState *env, \
t.VsrD(0) = xb->VsrD(0); \
} \
\
- vex_flag = fpscr_ve & vxsnan_flag; \
+ vex_flag = (env->fpscr & FP_VE) && vxsnan_flag; \
if (vxsnan_flag) { \
float_invalid_op_vxsnan(env, GETPC()); \
} \
@@ -3320,7 +3320,7 @@ void helper_xsrqpi(CPUPPCState *env, uint32_t opcode,
if (r == 0 && rmc == 0) {
rmode = float_round_ties_away;
} else if (r == 0 && rmc == 0x3) {
- rmode = fpscr_rn;
+ rmode = env->fpscr & FP_RN;
} else if (r == 1) {
switch (rmc) {
case 0:
@@ -3374,7 +3374,7 @@ void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode,
if (r == 0 && rmc == 0) {
rmode = float_round_ties_away;
} else if (r == 0 && rmc == 0x3) {
- rmode = fpscr_rn;
+ rmode = env->fpscr & FP_RN;
} else if (r == 1) {
switch (rmc) {
case 0:
--
2.32.0
next prev parent reply other threads:[~2022-05-05 19:32 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-05 18:49 [PULL 00/30] ppc queue Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 01/30] target/ppc: initialize 'val' union in kvm_get_one_spr() Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 02/30] target/ppc: init 'lpcr' in kvmppc_enable_cap_large_decr() Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 03/30] target/ppc: init 'sregs' in kvmppc_put_books_sregs() Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 04/30] target/ppc: init 'rmmu_info' in kvm_get_radix_page_info() Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 05/30] target/ppc: Fix BookE debug interrupt generation Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 06/30] vhost-user: Use correct macro name TARGET_PPC64 Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 07/30] ppc/xive: Always recompute the PIPR when pushing an OS context Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 08/30] ppc/xive: Update the state of the External interrupt signal Daniel Henrique Barboza
2022-05-05 18:49 ` Daniel Henrique Barboza [this message]
2022-05-05 18:49 ` [PULL 10/30] target/ppc: Remove unused msr_* macros Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 11/30] target/ppc: Remove msr_pr macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 12/30] target/ppc: Remove msr_le macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 13/30] target/ppc: Remove msr_ds macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 14/30] target/ppc: Remove msr_ile macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 15/30] target/ppc: Remove msr_ee macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 16/30] target/ppc: Remove msr_ce macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 17/30] target/ppc: Remove msr_pow macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 18/30] target/ppc: Remove msr_me macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 19/30] target/ppc: Remove msr_gs macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 20/30] target/ppc: Remove msr_fp macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 21/30] target/ppc: Remove msr_cm macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 22/30] target/ppc: Remove msr_ir macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 23/30] target/ppc: Remove msr_dr macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 24/30] target/ppc: Remove msr_ep macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 25/30] target/ppc: Remove msr_fe0 and msr_fe1 macros Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 26/30] target/ppc: Remove msr_ts macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 27/30] target/ppc: Remove msr_hv macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 28/30] target/ppc: Remove msr_de macro Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 29/30] target/ppc: Add unused msr bits FIELDs Daniel Henrique Barboza
2022-05-05 18:49 ` [PULL 30/30] target/ppc: Change MSR_* to follow POWER ISA numbering convention Daniel Henrique Barboza
2022-05-06 4:17 ` [PULL 00/30] ppc queue Richard Henderson
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