From: kernel test robot <lkp@intel.com>
To: Akhil R <akhilrajeev@nvidia.com>
Cc: kbuild-all@lists.01.org,
Linux Memory Management List <linux-mm@kvack.org>,
Vinod Koul <vkoul@kernel.org>,
Pavan Kunapuli <pkunapuli@nvidia.com>,
Rajesh Gumasta <rgumasta@nvidia.com>,
Jon Hunter <jonathanh@nvidia.com>,
Dmitry Osipenko <digetx@gmail.com>
Subject: [linux-next:master 2448/9759] drivers/dma/tegra186-gpc-dma.c:1365:31: error: 'struct iommu_fwspec' has no member named 'ids'
Date: Sun, 8 May 2022 00:24:04 +0800 [thread overview]
Message-ID: <202205080028.WTvTPW33-lkp@intel.com> (raw)
tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head: 38a288f5941ef03752887ad86f2d85442358c99a
commit: ee17028009d49fffed8cc963455d33b1fd3f1d08 [2448/9759] dmaengine: tegra: Add tegra gpcdma driver
config: alpha-randconfig-r026-20220507 (https://download.01.org/0day-ci/archive/20220508/202205080028.WTvTPW33-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 11.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=ee17028009d49fffed8cc963455d33b1fd3f1d08
git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
git fetch --no-tags linux-next master
git checkout ee17028009d49fffed8cc963455d33b1fd3f1d08
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross W=1 O=build_dir ARCH=alpha SHELL=/bin/bash drivers/dma/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_probe':
>> drivers/dma/tegra186-gpc-dma.c:1365:31: error: 'struct iommu_fwspec' has no member named 'ids'
1365 | stream_id = iommu_spec->ids[0] & 0xffff;
| ^~
vim +1365 drivers/dma/tegra186-gpc-dma.c
1325
1326 static int tegra_dma_probe(struct platform_device *pdev)
1327 {
1328 const struct tegra_dma_chip_data *cdata = NULL;
1329 struct iommu_fwspec *iommu_spec;
1330 unsigned int stream_id, i;
1331 struct tegra_dma *tdma;
1332 struct resource *res;
1333 int ret;
1334
1335 cdata = of_device_get_match_data(&pdev->dev);
1336
1337 tdma = devm_kzalloc(&pdev->dev,
1338 struct_size(tdma, channels, cdata->nr_channels),
1339 GFP_KERNEL);
1340 if (!tdma)
1341 return -ENOMEM;
1342
1343 tdma->dev = &pdev->dev;
1344 tdma->chip_data = cdata;
1345 platform_set_drvdata(pdev, tdma);
1346
1347 tdma->base_addr = devm_platform_ioremap_resource(pdev, 0);
1348 if (IS_ERR(tdma->base_addr))
1349 return PTR_ERR(tdma->base_addr);
1350
1351 tdma->rst = devm_reset_control_get_exclusive(&pdev->dev, "gpcdma");
1352 if (IS_ERR(tdma->rst)) {
1353 return dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst),
1354 "Missing controller reset\n");
1355 }
1356 reset_control_reset(tdma->rst);
1357
1358 tdma->dma_dev.dev = &pdev->dev;
1359
1360 iommu_spec = dev_iommu_fwspec_get(&pdev->dev);
1361 if (!iommu_spec) {
1362 dev_err(&pdev->dev, "Missing iommu stream-id\n");
1363 return -EINVAL;
1364 }
> 1365 stream_id = iommu_spec->ids[0] & 0xffff;
1366
1367 INIT_LIST_HEAD(&tdma->dma_dev.channels);
1368 for (i = 0; i < cdata->nr_channels; i++) {
1369 struct tegra_dma_channel *tdc = &tdma->channels[i];
1370
1371 tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET +
1372 i * cdata->channel_reg_size;
1373 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1374 if (!res) {
1375 dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1376 return -EINVAL;
1377 }
1378 tdc->irq = res->start;
1379 snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i);
1380
1381 tdc->tdma = tdma;
1382 tdc->id = i;
1383 tdc->slave_id = -1;
1384
1385 vchan_init(&tdc->vc, &tdma->dma_dev);
1386 tdc->vc.desc_free = tegra_dma_desc_free;
1387
1388 /* program stream-id for this channel */
1389 tegra_dma_program_sid(tdc, stream_id);
1390 tdc->stream_id = stream_id;
1391 }
1392
1393 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
1394 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
1395 dma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask);
1396 dma_cap_set(DMA_MEMSET, tdma->dma_dev.cap_mask);
1397 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
1398
1399 /*
1400 * Only word aligned transfers are supported. Set the copy
1401 * alignment shift.
1402 */
1403 tdma->dma_dev.copy_align = 2;
1404 tdma->dma_dev.fill_align = 2;
1405 tdma->dma_dev.device_alloc_chan_resources =
1406 tegra_dma_alloc_chan_resources;
1407 tdma->dma_dev.device_free_chan_resources =
1408 tegra_dma_free_chan_resources;
1409 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
1410 tdma->dma_dev.device_prep_dma_memcpy = tegra_dma_prep_dma_memcpy;
1411 tdma->dma_dev.device_prep_dma_memset = tegra_dma_prep_dma_memset;
1412 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
1413 tdma->dma_dev.device_config = tegra_dma_slave_config;
1414 tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
1415 tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
1416 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
1417 tdma->dma_dev.device_pause = tegra_dma_device_pause;
1418 tdma->dma_dev.device_resume = tegra_dma_device_resume;
1419 tdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize;
1420 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1421
1422 ret = dma_async_device_register(&tdma->dma_dev);
1423 if (ret < 0) {
1424 dev_err_probe(&pdev->dev, ret,
1425 "GPC DMA driver registration failed\n");
1426 return ret;
1427 }
1428
1429 ret = of_dma_controller_register(pdev->dev.of_node,
1430 tegra_dma_of_xlate, tdma);
1431 if (ret < 0) {
1432 dev_err_probe(&pdev->dev, ret,
1433 "GPC DMA OF registration failed\n");
1434
1435 dma_async_device_unregister(&tdma->dma_dev);
1436 return ret;
1437 }
1438
1439 dev_info(&pdev->dev, "GPC DMA driver register %d channels\n",
1440 cdata->nr_channels);
1441
1442 return 0;
1443 }
1444
--
0-DAY CI Kernel Test Service
https://01.org/lkp
reply other threads:[~2022-05-07 16:25 UTC|newest]
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