From: Rob Herring <robh@kernel.org>
To: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
michals@xilinx.com, lorenzo.pieralisi@arm.com,
bhelgaas@google.com, devicetree@vger.kernel.org
Subject: Re: [PATCH v2] dt-bindings: PCI: xilinx-cpm: Fix reg property order
Date: Wed, 1 Jun 2022 14:55:23 -0500 [thread overview]
Message-ID: <20220601195523.GA328031-robh@kernel.org> (raw)
In-Reply-To: <20220516102217.25960-1-bharat.kumar.gogada@xilinx.com>
On Mon, 16 May 2022 15:52:17 +0530, Bharat Kumar Gogada wrote:
> All existing vendor DTSes are using "cpm_slcr" reg followed by "cfg" reg.
>
> This order is also suggested by node name which is pcie@fca10000 which
> suggests that cpm_slcr register should be the first.
>
> Driver itself is using devm_platform_ioremap_resource_byname() for both
> names that's why there is no functional change even on description which
> are using current order.
>
> But still prefer to change order to cover currently used description.
> Fixes: e22fadb1d014 ("PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port")
>
> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> ---
> .../devicetree/bindings/pci/xilinx-versal-cpm.yaml | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
Applied, thanks!
next prev parent reply other threads:[~2022-06-01 20:45 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-16 10:22 [PATCH v2] dt-bindings: PCI: xilinx-cpm: Fix reg property order Bharat Kumar Gogada
2022-05-16 11:17 ` Michal Simek
2022-05-25 11:03 ` Bharat Kumar Gogada
2022-06-01 19:53 ` Rob Herring
2022-06-01 19:55 ` Rob Herring [this message]
2022-06-03 4:52 ` Bharat Kumar Gogada
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