From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 616B1C433EF for ; Tue, 7 Jun 2022 16:37:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232812AbiFGQhQ (ORCPT ); Tue, 7 Jun 2022 12:37:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345057AbiFGQhO (ORCPT ); Tue, 7 Jun 2022 12:37:14 -0400 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73C10B0D20 for ; Tue, 7 Jun 2022 09:37:09 -0700 (PDT) Received: from fraeml701-chm.china.huawei.com (unknown [172.18.147.206]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4LHbZg0GGjz6817f; Wed, 8 Jun 2022 00:35:55 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml701-chm.china.huawei.com (10.206.15.50) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2375.24; Tue, 7 Jun 2022 18:37:06 +0200 Received: from localhost (10.202.226.42) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Tue, 7 Jun 2022 17:37:04 +0100 Date: Tue, 7 Jun 2022 17:37:02 +0100 From: Jonathan Cameron To: Ben Widawsky CC: , "Michael S . Tsirkin" , "Paolo Bonzini" , , , , Marcel Apfelbaum , Igor Mammedov , Markus Armbruster , Mark Cave-Ayland , "Adam Manzanares" , Tong Zhang , Shameerali Kolothum Thodi Subject: Re: [PATCH v3] hw/cxl: Fix missing write mask for HDM decoder target list registers Message-ID: <20220607173702.00005ccf@Huawei.com> In-Reply-To: <20220607161928.364mrju2mvzcvs56@bwidawsk-mobl5> References: <20220607160747.21084-1-Jonathan.Cameron@huawei.com> <20220607161928.364mrju2mvzcvs56@bwidawsk-mobl5> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.29; i686-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.202.226.42] X-ClientProxiedBy: lhreml732-chm.china.huawei.com (10.201.108.83) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org On Tue, 7 Jun 2022 09:19:28 -0700 Ben Widawsky wrote: > On 22-06-07 17:07:47, Jonathan Cameron wrote: > > Without being able to write these registers, no interleaving is possible. > > More refined checks of HDM register state on commit to follow. > > > > Signed-off-by: Jonathan Cameron > > --- > > v3: Actually pass the parameter to the call... > > v2: (Ben Widawsky) > > - Correctly set a tighter write mask for the endpoint devices where this > > register has a different use. > > > > hw/cxl/cxl-component-utils.c | 11 +++++++++-- > > 1 file changed, 9 insertions(+), 2 deletions(-) > > > > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c > > index 7985c9bfca..2208284ee6 100644 > > --- a/hw/cxl/cxl-component-utils.c > > +++ b/hw/cxl/cxl-component-utils.c > > @@ -154,7 +154,8 @@ static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk) > > reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00; > > } > > > > -static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk) > > +static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, > > + enum reg_type type) > > { > > int decoder_count = 1; > > int i; > > @@ -174,6 +175,12 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk) > > write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000; > > write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff; > > write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff; > > + if (type == CXL2_DEVICE) { > > + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xf0000000; > > + } else { > > + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xffffffff; > > + } > > + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff; > > Should it be (type == CXL2_DEVICE || type == CXL2_TYPE3_DEVICE) ? Good point, but also for consistency I think we need type == CXL2_LOGICAL_DEVICE as well. We will only exercise the match to CXL2_TYPE3_DEVICE currently as we don't have any emulation for MLDs (and hence LD) or type 1/2 devices (CXL2_DEVICE). I'll send a v4 out tomorrow. > > Otherwise, > Reviewed-by: Ben Widawsky > > > } > > } > > > > @@ -239,7 +246,7 @@ void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk > > } > > > > init_cap_reg(HDM, 5, 1); > > - hdm_init_common(reg_state, write_msk); > > + hdm_init_common(reg_state, write_msk, type); > > > > if (caps < 5) { > > return; > > -- > > 2.32.0 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB0F8C433EF for ; Tue, 7 Jun 2022 16:38:30 +0000 (UTC) Received: from localhost ([::1]:45832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nycDt-0005Ch-88 for qemu-devel@archiver.kernel.org; Tue, 07 Jun 2022 12:38:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60022) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nycCh-0004V3-CF for qemu-devel@nongnu.org; Tue, 07 Jun 2022 12:37:16 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]:2606) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nycCd-0001rH-UK for qemu-devel@nongnu.org; Tue, 07 Jun 2022 12:37:15 -0400 Received: from fraeml701-chm.china.huawei.com (unknown [172.18.147.206]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4LHbZg0GGjz6817f; Wed, 8 Jun 2022 00:35:55 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml701-chm.china.huawei.com (10.206.15.50) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2375.24; Tue, 7 Jun 2022 18:37:06 +0200 Received: from localhost (10.202.226.42) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Tue, 7 Jun 2022 17:37:04 +0100 Date: Tue, 7 Jun 2022 17:37:02 +0100 To: Ben Widawsky CC: , "Michael S . Tsirkin" , "Paolo Bonzini" , , , , Marcel Apfelbaum , Igor Mammedov , Markus Armbruster , Mark Cave-Ayland , "Adam Manzanares" , Tong Zhang , Shameerali Kolothum Thodi Subject: Re: [PATCH v3] hw/cxl: Fix missing write mask for HDM decoder target list registers Message-ID: <20220607173702.00005ccf@Huawei.com> In-Reply-To: <20220607161928.364mrju2mvzcvs56@bwidawsk-mobl5> References: <20220607160747.21084-1-Jonathan.Cameron@huawei.com> <20220607161928.364mrju2mvzcvs56@bwidawsk-mobl5> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.29; i686-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.202.226.42] X-ClientProxiedBy: lhreml732-chm.china.huawei.com (10.201.108.83) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Jonathan Cameron From: Jonathan Cameron via On Tue, 7 Jun 2022 09:19:28 -0700 Ben Widawsky wrote: > On 22-06-07 17:07:47, Jonathan Cameron wrote: > > Without being able to write these registers, no interleaving is possible. > > More refined checks of HDM register state on commit to follow. > > > > Signed-off-by: Jonathan Cameron > > --- > > v3: Actually pass the parameter to the call... > > v2: (Ben Widawsky) > > - Correctly set a tighter write mask for the endpoint devices where this > > register has a different use. > > > > hw/cxl/cxl-component-utils.c | 11 +++++++++-- > > 1 file changed, 9 insertions(+), 2 deletions(-) > > > > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c > > index 7985c9bfca..2208284ee6 100644 > > --- a/hw/cxl/cxl-component-utils.c > > +++ b/hw/cxl/cxl-component-utils.c > > @@ -154,7 +154,8 @@ static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk) > > reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00; > > } > > > > -static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk) > > +static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, > > + enum reg_type type) > > { > > int decoder_count = 1; > > int i; > > @@ -174,6 +175,12 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk) > > write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000; > > write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff; > > write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff; > > + if (type == CXL2_DEVICE) { > > + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xf0000000; > > + } else { > > + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xffffffff; > > + } > > + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff; > > Should it be (type == CXL2_DEVICE || type == CXL2_TYPE3_DEVICE) ? Good point, but also for consistency I think we need type == CXL2_LOGICAL_DEVICE as well. We will only exercise the match to CXL2_TYPE3_DEVICE currently as we don't have any emulation for MLDs (and hence LD) or type 1/2 devices (CXL2_DEVICE). I'll send a v4 out tomorrow. > > Otherwise, > Reviewed-by: Ben Widawsky > > > } > > } > > > > @@ -239,7 +246,7 @@ void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk > > } > > > > init_cap_reg(HDM, 5, 1); > > - hdm_init_common(reg_state, write_msk); > > + hdm_init_common(reg_state, write_msk, type); > > > > if (caps < 5) { > > return; > > -- > > 2.32.0 > >