From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 824A9C433EF for ; Thu, 9 Jun 2022 07:53:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233090AbiFIHxN (ORCPT ); Thu, 9 Jun 2022 03:53:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232357AbiFIHxM (ORCPT ); Thu, 9 Jun 2022 03:53:12 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 630B61E3028; Thu, 9 Jun 2022 00:53:10 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id F2113B82C3D; Thu, 9 Jun 2022 07:53:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5C5D4C34114; Thu, 9 Jun 2022 07:53:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1654761187; bh=P3FLNlZhGb3NkhkHCxICHx9Dpls3bm2gQnBATFpOF5c=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=GhgjJQ9I0cybj/OzgI8ZYMTl0Lsr9RRvQ/YBDZuyJTNdw9DPyzNfGsyCx29xiBruO jOymaSYJ57LUxHpOBz/qfP+SJawhMJZP2YLp5pEkieB2cu+4Ysge5HOICBbqxivd56 E3JOxpLkNo8quJvYJlqsfcUeAa5cs6usYEXMbdhq+WFAlhmFv8GDnY3rNKiidtZbHF +9cEtD27eLK32vAG/7USmTQtoEKN/Zg2uwK1TolmlCyPyJFICO77SZdubcjSpS4qLv tz/EG+x87joXiVN/CpnwFR+mBIowfJ+6lMWE1pntu8xLXN7AYMQ0wnsSJVmTUXIJPl VQ/PN/XQ9JP2A== Date: Thu, 9 Jun 2022 13:22:54 +0530 From: Manivannan Sadhasivam To: Ansuel Smith Cc: Andy Gross , Bjorn Andersson , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 1/3] mtd: nand: raw: qcom_nandc: add support for unprotected spare data pages Message-ID: <20220609075254.GC2758@thinkpad> References: <20220608001030.18813-1-ansuelsmth@gmail.com> <20220608001030.18813-2-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220608001030.18813-2-ansuelsmth@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed, Jun 08, 2022 at 02:10:28AM +0200, Ansuel Smith wrote: > IPQ8064 nand have special pages where a different layout scheme is used. > These special page are used by boot partition and on reading them > lots of warning are reported about wrong ECC data and if written to > results in broken data and not bootable device. > > The layout scheme used by these special page consist in using 512 bytes > as the codeword size (even for the last codeword) while writing to CFG0 > register. This forces the NAND controller to unprotect the 4 bytes of > spare data. > > Since the kernel is unaware of this different layout for these special > page, it does try to protect the spare data too during read/write and > warn about CRC errors. > > Add support for this by permitting the user to declare these special > pages in dts by declaring offset and size of the partition. The driver > internally will convert these value to nand pages. > > On user read/write the page is checked and if it's a boot page the > correct layout is used. > > Signed-off-by: Ansuel Smith > --- > drivers/mtd/nand/raw/qcom_nandc.c | 174 +++++++++++++++++++++++++++++- > 1 file changed, 169 insertions(+), 5 deletions(-) > > diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c > index 1a77542c6d67..06ee9a836a3b 100644 > --- a/drivers/mtd/nand/raw/qcom_nandc.c > +++ b/drivers/mtd/nand/raw/qcom_nandc.c > @@ -80,8 +80,10 @@ > #define DISABLE_STATUS_AFTER_WRITE 4 > #define CW_PER_PAGE 6 > #define UD_SIZE_BYTES 9 > +#define UD_SIZE_BYTES_MASK GENMASK(18, 9) > #define ECC_PARITY_SIZE_BYTES_RS 19 > #define SPARE_SIZE_BYTES 23 > +#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23) > #define NUM_ADDR_CYCLES 27 > #define STATUS_BFR_READ 30 > #define SET_RD_MODE_AFTER_STATUS 31 > @@ -102,6 +104,7 @@ > #define ECC_MODE 4 > #define ECC_PARITY_SIZE_BYTES_BCH 8 > #define ECC_NUM_DATA_BYTES 16 > +#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16) > #define ECC_FORCE_CLK_OPEN 30 > > /* NAND_DEV_CMD1 bits */ > @@ -418,6 +421,19 @@ struct qcom_nand_controller { > const struct qcom_nandc_props *props; > }; > > +/* > + * NAND special boot partitions > + * > + * @page_offset: offset of the partition where spare data is not protected > + * by ECC (value in pages) s/page_offset/offset > + * @page_offset: size of the partition where spare data is not protected > + * by ECC (value in pages) s/page_offset/size > + */ > +struct qcom_nand_boot_partition { > + u32 page_offset; > + u32 page_size; same here > +}; > + > /* > * NAND chip structure > * > @@ -444,6 +460,13 @@ struct qcom_nand_controller { > * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for > * ecc/non-ecc mode for the current nand flash > * device > + * > + * @codeword_fixup: keep track of the current layout used by > + * the driver for read/write operation. > + * @nr_boot_partitions: count of the boot partitions where spare data is not > + * protected by ECC Align the Kdoc comments w.r.t other members. > + * @boot_pages: array of boot partitions where offset and size of the > + * boot partitions are stored s/boot_pages/boot_partitions > */ > struct qcom_nand_host { > struct nand_chip chip; > @@ -466,6 +489,10 @@ struct qcom_nand_host { > u32 ecc_bch_cfg; > u32 clrflashstatus; > u32 clrreadstatus; > + > + bool codeword_fixup; > + int nr_boot_partitions; > + struct qcom_nand_boot_partition *boot_partitions; > }; > > /* > @@ -475,6 +502,7 @@ struct qcom_nand_host { > * @is_bam - whether NAND controller is using BAM > * @is_qpic - whether NAND CTRL is part of qpic IP > * @qpic_v2 - flag to indicate QPIC IP version 2 > + * @use_codeword_fixup - whether NAND has different layout for boot partitions > * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset > */ > struct qcom_nandc_props { > @@ -482,6 +510,7 @@ struct qcom_nandc_props { > bool is_bam; > bool is_qpic; > bool qpic_v2; > + bool use_codeword_fixup; > u32 dev_cmd_reg_start; > }; > > @@ -1701,7 +1730,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip, > data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); > oob_size1 = host->bbm_size; > > - if (qcom_nandc_is_last_cw(ecc, cw)) { > + if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { > data_size2 = ecc->size - data_size1 - > ((ecc->steps - 1) * 4); > oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw + > @@ -1782,7 +1811,7 @@ check_for_erased_page(struct qcom_nand_host *host, u8 *data_buf, > } > > for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) { > - if (qcom_nandc_is_last_cw(ecc, cw)) { > + if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { > data_size = ecc->size - ((ecc->steps - 1) * 4); > oob_size = (ecc->steps * 4) + host->ecc_bytes_hw; > } else { > @@ -1940,7 +1969,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf, > for (i = 0; i < ecc->steps; i++) { > int data_size, oob_size; > > - if (qcom_nandc_is_last_cw(ecc, i)) { > + if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { > data_size = ecc->size - ((ecc->steps - 1) << 2); > oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + > host->spare_bytes; > @@ -2037,6 +2066,55 @@ static int copy_last_cw(struct qcom_nand_host *host, int page) > return ret; > } > > +static bool > +qcom_nandc_is_boot_page(struct qcom_nand_host *host, int page) Move function name to previous line. If it exceeds 100 lines then wrap arguments. s/qcom_nandc_is_boot_page/qcom_nandc_is_boot_partition > +{ > + struct qcom_nand_boot_partition *boot_partition; > + u32 start, end; > + int i; > + > + for (i = 0; i < host->nr_boot_partitions; i++) { > + boot_partition = &host->boot_partitions[i]; > + start = boot_partition->page_offset; > + end = start + boot_partition->page_size; > + > + /* Boot pages are normally at the start of Block comments should start with: /* * ... Also, are you sure that only few pages in the partitions have different layout and not all pages? If not, then this comment needs to be reworded. > + * the nand in various partition. > + * Check the page from the boot page end first > + * to save one extra check and optimize this > + * in case real no-boot partition are used. > + */ > + if (page < end && page >= start) > + return true; > + } > + > + return false; > +} > + > +static void > +qcom_nandc_codeword_fixup(struct qcom_nand_host *host, int page) > +{ > + bool codeword_fixup = qcom_nandc_is_boot_page(host, page); > + > + /* Skip conf write if we are already in the correct mode */ > + if (codeword_fixup == host->codeword_fixup) > + return; > + > + host->codeword_fixup = codeword_fixup; > + > + host->cw_data = codeword_fixup ? 512 : 516; > + host->spare_bytes = host->cw_size - host->ecc_bytes_hw - > + host->bbm_size - host->cw_data; > + > + host->cfg0 &= ~(SPARE_SIZE_BYTES_MASK | UD_SIZE_BYTES_MASK); > + host->cfg0 |= host->spare_bytes << SPARE_SIZE_BYTES | > + host->cw_data << UD_SIZE_BYTES; > + > + host->ecc_bch_cfg &= ~ECC_NUM_DATA_BYTES_MASK; > + host->ecc_bch_cfg |= host->cw_data << ECC_NUM_DATA_BYTES; > + host->ecc_buf_cfg = (codeword_fixup ? 0x1ff : 0x203) << NUM_STEPS; s/1ff/(512 - 1) s/203/(516 - 1) > +} > + > /* implements ecc->read_page() */ > static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf, > int oob_required, int page) > @@ -2045,6 +2123,9 @@ static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf, > struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); > u8 *data_buf, *oob_buf = NULL; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > nand_read_page_op(chip, page, 0, NULL, 0); > data_buf = buf; > oob_buf = oob_required ? chip->oob_poi : NULL; > @@ -2064,6 +2145,9 @@ static int qcom_nandc_read_page_raw(struct nand_chip *chip, uint8_t *buf, > int cw, ret; > u8 *data_buf = buf, *oob_buf = chip->oob_poi; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > for (cw = 0; cw < ecc->steps; cw++) { > ret = qcom_nandc_read_cw_raw(mtd, chip, data_buf, oob_buf, > page, cw); > @@ -2084,6 +2168,9 @@ static int qcom_nandc_read_oob(struct nand_chip *chip, int page) > struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); > struct nand_ecc_ctrl *ecc = &chip->ecc; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > clear_read_regs(nandc); > clear_bam_transaction(nandc); > > @@ -2104,6 +2191,9 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const uint8_t *buf, > u8 *data_buf, *oob_buf; > int i, ret; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > nand_prog_page_begin_op(chip, page, 0, NULL, 0); > > clear_read_regs(nandc); > @@ -2119,7 +2209,7 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const uint8_t *buf, > for (i = 0; i < ecc->steps; i++) { > int data_size, oob_size; > > - if (qcom_nandc_is_last_cw(ecc, i)) { > + if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { > data_size = ecc->size - ((ecc->steps - 1) << 2); > oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + > host->spare_bytes; > @@ -2176,6 +2266,9 @@ static int qcom_nandc_write_page_raw(struct nand_chip *chip, > u8 *data_buf, *oob_buf; > int i, ret; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > nand_prog_page_begin_op(chip, page, 0, NULL, 0); > clear_read_regs(nandc); > clear_bam_transaction(nandc); > @@ -2194,7 +2287,7 @@ static int qcom_nandc_write_page_raw(struct nand_chip *chip, > data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); > oob_size1 = host->bbm_size; > > - if (qcom_nandc_is_last_cw(ecc, i)) { > + if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { > data_size2 = ecc->size - data_size1 - > ((ecc->steps - 1) << 2); > oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + > @@ -2254,6 +2347,9 @@ static int qcom_nandc_write_oob(struct nand_chip *chip, int page) > int data_size, oob_size; > int ret; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > host->use_ecc = true; > clear_bam_transaction(nandc); > > @@ -2902,6 +2998,71 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc) > > static const char * const probes[] = { "cmdlinepart", "ofpart", "qcomsmem", NULL }; > > +static int qcom_nand_host_parse_boot_partitions(struct qcom_nand_controller *nandc, > + struct qcom_nand_host *host, > + struct device_node *dn) > +{ > + struct nand_chip *chip = &host->chip; > + struct mtd_info *mtd = nand_to_mtd(chip); > + struct qcom_nand_boot_partition *boot_partition; > + struct device *dev = nandc->dev; > + int partitions_count, i, j, ret; > + > + if (!nandc->props->use_codeword_fixup) > + return 0; Move this check to caller as I suggested previously. > + > + if (!of_find_property(dn, "qcom,boot-partitions", NULL)) > + return 0; > + > + partitions_count = of_property_count_u32_elems(dn, "qcom,boot-partitions"); > + if (partitions_count < 0) { partitions_count <= 0 > + dev_err(dev, "Error parsing boot partition."); Add newline at the end of error message > + return ret; > + } > + > + host->nr_boot_partitions = partitions_count / 2; > + host->boot_partitions = devm_kcalloc(dev, host->nr_boot_partitions, > + sizeof(*host->boot_partitions), GFP_KERNEL); > + if (!host->boot_partitions) host->nr_boot_partitions = 0; > + return -ENOMEM; > + > + for (i = 0, j = 0; i < host->nr_boot_partitions; i++, j += 2) { > + boot_partition = &host->boot_partitions[i]; > + > + ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j, > + &boot_partition->page_offset); > + if (ret) { > + dev_err(dev, "Error parsing boot partition offset at index %d", i); Add newline at the end of error message. Do the same for all error prints. > + return ret; > + } > + > + if (boot_partition->page_offset % mtd->writesize) { > + dev_err(dev, "Boot partition offset not multiple of writesize at index %i", > + i); > + return -EINVAL; > + } > + /* Convert offset to nand pages */ s/pages/partitions > + boot_partition->page_offset /= mtd->writesize; s/page_offset/offset > + > + ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j + 1, > + &boot_partition->page_size); > + if (ret) { > + dev_err(dev, "Error parsing boot partition size at index %d", i); > + return ret; > + } > + > + if (boot_partition->page_size % mtd->writesize) { s/page_size/size here and below > + dev_err(dev, "Boot partition size not multiple of writesize at index %i", > + i); > + return -EINVAL; > + } > + /* Convert size to nand pages */ s/pages/partitions Thanks, Mani > + boot_partition->page_size /= mtd->writesize; > + } > + > + return 0; > +} > + > static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, > struct qcom_nand_host *host, > struct device_node *dn) > @@ -2970,6 +3131,8 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, > if (ret) > nand_cleanup(chip); > > + qcom_nand_host_parse_boot_partitions(nandc, host, dn); > + > return ret; > } > > @@ -3135,6 +3298,7 @@ static int qcom_nandc_remove(struct platform_device *pdev) > static const struct qcom_nandc_props ipq806x_nandc_props = { > .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT), > .is_bam = false, > + .use_codeword_fixup = true, > .dev_cmd_reg_start = 0x0, > }; > > -- > 2.36.1 > -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) 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esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nzCyh-0000JR-DH; Thu, 09 Jun 2022 07:53:15 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nzCyc-0000Fm-JQ for linux-mtd@lists.infradead.org; Thu, 09 Jun 2022 07:53:13 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id E6619B829F9; Thu, 9 Jun 2022 07:53:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5C5D4C34114; Thu, 9 Jun 2022 07:53:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1654761187; bh=P3FLNlZhGb3NkhkHCxICHx9Dpls3bm2gQnBATFpOF5c=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=GhgjJQ9I0cybj/OzgI8ZYMTl0Lsr9RRvQ/YBDZuyJTNdw9DPyzNfGsyCx29xiBruO jOymaSYJ57LUxHpOBz/qfP+SJawhMJZP2YLp5pEkieB2cu+4Ysge5HOICBbqxivd56 E3JOxpLkNo8quJvYJlqsfcUeAa5cs6usYEXMbdhq+WFAlhmFv8GDnY3rNKiidtZbHF +9cEtD27eLK32vAG/7USmTQtoEKN/Zg2uwK1TolmlCyPyJFICO77SZdubcjSpS4qLv tz/EG+x87joXiVN/CpnwFR+mBIowfJ+6lMWE1pntu8xLXN7AYMQ0wnsSJVmTUXIJPl VQ/PN/XQ9JP2A== Date: Thu, 9 Jun 2022 13:22:54 +0530 From: Manivannan Sadhasivam To: Ansuel Smith Cc: Andy Gross , Bjorn Andersson , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 1/3] mtd: nand: raw: qcom_nandc: add support for unprotected spare data pages Message-ID: <20220609075254.GC2758@thinkpad> References: <20220608001030.18813-1-ansuelsmth@gmail.com> <20220608001030.18813-2-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220608001030.18813-2-ansuelsmth@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220609_005310_992573_7C658652 X-CRM114-Status: GOOD ( 52.80 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org T24gV2VkLCBKdW4gMDgsIDIwMjIgYXQgMDI6MTA6MjhBTSArMDIwMCwgQW5zdWVsIFNtaXRoIHdy b3RlOgo+IElQUTgwNjQgbmFuZCBoYXZlIHNwZWNpYWwgcGFnZXMgd2hlcmUgYSBkaWZmZXJlbnQg bGF5b3V0IHNjaGVtZSBpcyB1c2VkLgo+IFRoZXNlIHNwZWNpYWwgcGFnZSBhcmUgdXNlZCBieSBi b290IHBhcnRpdGlvbiBhbmQgb24gcmVhZGluZyB0aGVtCj4gbG90cyBvZiB3YXJuaW5nIGFyZSBy ZXBvcnRlZCBhYm91dCB3cm9uZyBFQ0MgZGF0YSBhbmQgaWYgd3JpdHRlbiB0bwo+IHJlc3VsdHMg aW4gYnJva2VuIGRhdGEgYW5kIG5vdCBib290YWJsZSBkZXZpY2UuCj4gCj4gVGhlIGxheW91dCBz Y2hlbWUgdXNlZCBieSB0aGVzZSBzcGVjaWFsIHBhZ2UgY29uc2lzdCBpbiB1c2luZyA1MTIgYnl0 ZXMKPiBhcyB0aGUgY29kZXdvcmQgc2l6ZSAoZXZlbiBmb3IgdGhlIGxhc3QgY29kZXdvcmQpIHdo aWxlIHdyaXRpbmcgdG8gQ0ZHMAo+IHJlZ2lzdGVyLiBUaGlzIGZvcmNlcyB0aGUgTkFORCBjb250 cm9sbGVyIHRvIHVucHJvdGVjdCB0aGUgNCBieXRlcyBvZgo+IHNwYXJlIGRhdGEuCj4gCj4gU2lu Y2UgdGhlIGtlcm5lbCBpcyB1bmF3YXJlIG9mIHRoaXMgZGlmZmVyZW50IGxheW91dCBmb3IgdGhl c2Ugc3BlY2lhbAo+IHBhZ2UsIGl0IGRvZXMgdHJ5IHRvIHByb3RlY3QgdGhlIHNwYXJlIGRhdGEg dG9vIGR1cmluZyByZWFkL3dyaXRlIGFuZAo+IHdhcm4gYWJvdXQgQ1JDIGVycm9ycy4KPiAKPiBB ZGQgc3VwcG9ydCBmb3IgdGhpcyBieSBwZXJtaXR0aW5nIHRoZSB1c2VyIHRvIGRlY2xhcmUgdGhl c2Ugc3BlY2lhbAo+IHBhZ2VzIGluIGR0cyBieSBkZWNsYXJpbmcgb2Zmc2V0IGFuZCBzaXplIG9m IHRoZSBwYXJ0aXRpb24uIFRoZSBkcml2ZXIKPiBpbnRlcm5hbGx5IHdpbGwgY29udmVydCB0aGVz ZSB2YWx1ZSB0byBuYW5kIHBhZ2VzLgo+IAo+IE9uIHVzZXIgcmVhZC93cml0ZSB0aGUgcGFnZSBp cyBjaGVja2VkIGFuZCBpZiBpdCdzIGEgYm9vdCBwYWdlIHRoZQo+IGNvcnJlY3QgbGF5b3V0IGlz IHVzZWQuCj4gCj4gU2lnbmVkLW9mZi1ieTogQW5zdWVsIFNtaXRoIDxhbnN1ZWxzbXRoQGdtYWls LmNvbT4KPiAtLS0KPiAgZHJpdmVycy9tdGQvbmFuZC9yYXcvcWNvbV9uYW5kYy5jIHwgMTc0ICsr KysrKysrKysrKysrKysrKysrKysrKysrKysrLQo+ICAxIGZpbGUgY2hhbmdlZCwgMTY5IGluc2Vy dGlvbnMoKyksIDUgZGVsZXRpb25zKC0pCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvbXRkL25h bmQvcmF3L3Fjb21fbmFuZGMuYyBiL2RyaXZlcnMvbXRkL25hbmQvcmF3L3Fjb21fbmFuZGMuYwo+ IGluZGV4IDFhNzc1NDJjNmQ2Ny4uMDZlZTlhODM2YTNiIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMv bXRkL25hbmQvcmF3L3Fjb21fbmFuZGMuYwo+ICsrKyBiL2RyaXZlcnMvbXRkL25hbmQvcmF3L3Fj b21fbmFuZGMuYwo+IEBAIC04MCw4ICs4MCwxMCBAQAo+ICAjZGVmaW5lCURJU0FCTEVfU1RBVFVT X0FGVEVSX1dSSVRFCTQKPiAgI2RlZmluZQlDV19QRVJfUEFHRQkJCTYKPiAgI2RlZmluZQlVRF9T SVpFX0JZVEVTCQkJOQo+ICsjZGVmaW5lCVVEX1NJWkVfQllURVNfTUFTSwkJR0VOTUFTSygxOCwg OSkKPiAgI2RlZmluZQlFQ0NfUEFSSVRZX1NJWkVfQllURVNfUlMJMTkKPiAgI2RlZmluZQlTUEFS RV9TSVpFX0JZVEVTCQkyMwo+ICsjZGVmaW5lCVNQQVJFX1NJWkVfQllURVNfTUFTSwkJR0VOTUFT SygyNiwgMjMpCj4gICNkZWZpbmUJTlVNX0FERFJfQ1lDTEVTCQkJMjcKPiAgI2RlZmluZQlTVEFU VVNfQkZSX1JFQUQJCQkzMAo+ICAjZGVmaW5lCVNFVF9SRF9NT0RFX0FGVEVSX1NUQVRVUwkzMQo+ IEBAIC0xMDIsNiArMTA0LDcgQEAKPiAgI2RlZmluZQlFQ0NfTU9ERQkJCTQKPiAgI2RlZmluZQlF Q0NfUEFSSVRZX1NJWkVfQllURVNfQkNICTgKPiAgI2RlZmluZQlFQ0NfTlVNX0RBVEFfQllURVMJ CTE2Cj4gKyNkZWZpbmUJRUNDX05VTV9EQVRBX0JZVEVTX01BU0sJCUdFTk1BU0soMjUsIDE2KQo+ ICAjZGVmaW5lCUVDQ19GT1JDRV9DTEtfT1BFTgkJMzAKPiAgCj4gIC8qIE5BTkRfREVWX0NNRDEg Yml0cyAqLwo+IEBAIC00MTgsNiArNDIxLDE5IEBAIHN0cnVjdCBxY29tX25hbmRfY29udHJvbGxl ciB7Cj4gIAljb25zdCBzdHJ1Y3QgcWNvbV9uYW5kY19wcm9wcyAqcHJvcHM7Cj4gIH07Cj4gIAo+ ICsvKgo+ICsgKiBOQU5EIHNwZWNpYWwgYm9vdCBwYXJ0aXRpb25zCj4gKyAqCj4gKyAqIEBwYWdl X29mZnNldDoJCW9mZnNldCBvZiB0aGUgcGFydGl0aW9uIHdoZXJlIHNwYXJlIGRhdGEgaXMgbm90 IHByb3RlY3RlZAo+ICsgKgkJCQlieSBFQ0MgKHZhbHVlIGluIHBhZ2VzKQoKcy9wYWdlX29mZnNl dC9vZmZzZXQKCj4gKyAqIEBwYWdlX29mZnNldDoJCXNpemUgb2YgdGhlIHBhcnRpdGlvbiB3aGVy ZSBzcGFyZSBkYXRhIGlzIG5vdCBwcm90ZWN0ZWQKPiArICoJCQkJYnkgRUNDICh2YWx1ZSBpbiBw YWdlcykKCnMvcGFnZV9vZmZzZXQvc2l6ZQoKPiArICovCj4gK3N0cnVjdCBxY29tX25hbmRfYm9v dF9wYXJ0aXRpb24gewo+ICsJdTMyIHBhZ2Vfb2Zmc2V0Owo+ICsJdTMyIHBhZ2Vfc2l6ZTsKCnNh bWUgaGVyZQoKPiArfTsKPiArCj4gIC8qCj4gICAqIE5BTkQgY2hpcCBzdHJ1Y3R1cmUKPiAgICoK PiBAQCAtNDQ0LDYgKzQ2MCwxMyBAQCBzdHJ1Y3QgcWNvbV9uYW5kX2NvbnRyb2xsZXIgewo+ICAg KiBAY2ZnMCwgY2ZnMSwgY2ZnMF9yYXcuLjoJTkFORGMgcmVnaXN0ZXIgY29uZmlndXJhdGlvbnMg bmVlZGVkIGZvcgo+ICAgKgkJCQllY2Mvbm9uLWVjYyBtb2RlIGZvciB0aGUgY3VycmVudCBuYW5k IGZsYXNoCj4gICAqCQkJCWRldmljZQo+ICsgKgo+ICsgKiBAY29kZXdvcmRfZml4dXA6CQlrZWVw IHRyYWNrIG9mIHRoZSBjdXJyZW50IGxheW91dCB1c2VkIGJ5Cj4gKyAqCQkJCXRoZSBkcml2ZXIg Zm9yIHJlYWQvd3JpdGUgb3BlcmF0aW9uLgo+ICsgKiBAbnJfYm9vdF9wYXJ0aXRpb25zOgkJY291 bnQgb2YgdGhlIGJvb3QgcGFydGl0aW9ucyB3aGVyZSBzcGFyZSBkYXRhIGlzIG5vdAo+ICsgKgkJ CQlwcm90ZWN0ZWQgYnkgRUNDCgpBbGlnbiB0aGUgS2RvYyBjb21tZW50cyB3LnIudCBvdGhlciBt ZW1iZXJzLgoKPiArICogQGJvb3RfcGFnZXM6CQkJYXJyYXkgb2YgYm9vdCBwYXJ0aXRpb25zIHdo ZXJlIG9mZnNldCBhbmQgc2l6ZSBvZiB0aGUKPiArICoJCQkJYm9vdCBwYXJ0aXRpb25zIGFyZSBz dG9yZWQKCnMvYm9vdF9wYWdlcy9ib290X3BhcnRpdGlvbnMKCj4gICAqLwo+ICBzdHJ1Y3QgcWNv bV9uYW5kX2hvc3Qgewo+ICAJc3RydWN0IG5hbmRfY2hpcCBjaGlwOwo+IEBAIC00NjYsNiArNDg5 LDEwIEBAIHN0cnVjdCBxY29tX25hbmRfaG9zdCB7Cj4gIAl1MzIgZWNjX2JjaF9jZmc7Cj4gIAl1 MzIgY2xyZmxhc2hzdGF0dXM7Cj4gIAl1MzIgY2xycmVhZHN0YXR1czsKPiArCj4gKwlib29sIGNv ZGV3b3JkX2ZpeHVwOwo+ICsJaW50IG5yX2Jvb3RfcGFydGl0aW9uczsKPiArCXN0cnVjdCBxY29t X25hbmRfYm9vdF9wYXJ0aXRpb24gKmJvb3RfcGFydGl0aW9uczsKPiAgfTsKPiAgCj4gIC8qCj4g QEAgLTQ3NSw2ICs1MDIsNyBAQCBzdHJ1Y3QgcWNvbV9uYW5kX2hvc3Qgewo+ICAgKiBAaXNfYmFt IC0gd2hldGhlciBOQU5EIGNvbnRyb2xsZXIgaXMgdXNpbmcgQkFNCj4gICAqIEBpc19xcGljIC0g d2hldGhlciBOQU5EIENUUkwgaXMgcGFydCBvZiBxcGljIElQCj4gICAqIEBxcGljX3YyIC0gZmxh ZyB0byBpbmRpY2F0ZSBRUElDIElQIHZlcnNpb24gMgo+ICsgKiBAdXNlX2NvZGV3b3JkX2ZpeHVw IC0gd2hldGhlciBOQU5EIGhhcyBkaWZmZXJlbnQgbGF5b3V0IGZvciBib290IHBhcnRpdGlvbnMK PiAgICogQGRldl9jbWRfcmVnX3N0YXJ0IC0gTkFORF9ERVZfQ01EXyogcmVnaXN0ZXJzIHN0YXJ0 aW5nIG9mZnNldAo+ICAgKi8KPiAgc3RydWN0IHFjb21fbmFuZGNfcHJvcHMgewo+IEBAIC00ODIs NiArNTEwLDcgQEAgc3RydWN0IHFjb21fbmFuZGNfcHJvcHMgewo+ICAJYm9vbCBpc19iYW07Cj4g IAlib29sIGlzX3FwaWM7Cj4gIAlib29sIHFwaWNfdjI7Cj4gKwlib29sIHVzZV9jb2Rld29yZF9m aXh1cDsKPiAgCXUzMiBkZXZfY21kX3JlZ19zdGFydDsKPiAgfTsKPiAgCj4gQEAgLTE3MDEsNyAr MTczMCw3IEBAIHFjb21fbmFuZGNfcmVhZF9jd19yYXcoc3RydWN0IG10ZF9pbmZvICptdGQsIHN0 cnVjdCBuYW5kX2NoaXAgKmNoaXAsCj4gIAlkYXRhX3NpemUxID0gbXRkLT53cml0ZXNpemUgLSBo b3N0LT5jd19zaXplICogKGVjYy0+c3RlcHMgLSAxKTsKPiAgCW9vYl9zaXplMSA9IGhvc3QtPmJi bV9zaXplOwo+ICAKPiAtCWlmIChxY29tX25hbmRjX2lzX2xhc3RfY3coZWNjLCBjdykpIHsKPiAr CWlmIChxY29tX25hbmRjX2lzX2xhc3RfY3coZWNjLCBjdykgJiYgIWhvc3QtPmNvZGV3b3JkX2Zp eHVwKSB7Cj4gIAkJZGF0YV9zaXplMiA9IGVjYy0+c2l6ZSAtIGRhdGFfc2l6ZTEgLQo+ICAJCQkg ICAgICgoZWNjLT5zdGVwcyAtIDEpICogNCk7Cj4gIAkJb29iX3NpemUyID0gKGVjYy0+c3RlcHMg KiA0KSArIGhvc3QtPmVjY19ieXRlc19odyArCj4gQEAgLTE3ODIsNyArMTgxMSw3IEBAIGNoZWNr X2Zvcl9lcmFzZWRfcGFnZShzdHJ1Y3QgcWNvbV9uYW5kX2hvc3QgKmhvc3QsIHU4ICpkYXRhX2J1 ZiwKPiAgCX0KPiAgCj4gIAlmb3JfZWFjaF9zZXRfYml0KGN3LCAmdW5jb3JyZWN0YWJsZV9jd3Ms IGVjYy0+c3RlcHMpIHsKPiAtCQlpZiAocWNvbV9uYW5kY19pc19sYXN0X2N3KGVjYywgY3cpKSB7 Cj4gKwkJaWYgKHFjb21fbmFuZGNfaXNfbGFzdF9jdyhlY2MsIGN3KSAmJiAhaG9zdC0+Y29kZXdv cmRfZml4dXApIHsKPiAgCQkJZGF0YV9zaXplID0gZWNjLT5zaXplIC0gKChlY2MtPnN0ZXBzIC0g MSkgKiA0KTsKPiAgCQkJb29iX3NpemUgPSAoZWNjLT5zdGVwcyAqIDQpICsgaG9zdC0+ZWNjX2J5 dGVzX2h3Owo+ICAJCX0gZWxzZSB7Cj4gQEAgLTE5NDAsNyArMTk2OSw3IEBAIHN0YXRpYyBpbnQg cmVhZF9wYWdlX2VjYyhzdHJ1Y3QgcWNvbV9uYW5kX2hvc3QgKmhvc3QsIHU4ICpkYXRhX2J1ZiwK PiAgCWZvciAoaSA9IDA7IGkgPCBlY2MtPnN0ZXBzOyBpKyspIHsKPiAgCQlpbnQgZGF0YV9zaXpl LCBvb2Jfc2l6ZTsKPiAgCj4gLQkJaWYgKHFjb21fbmFuZGNfaXNfbGFzdF9jdyhlY2MsIGkpKSB7 Cj4gKwkJaWYgKHFjb21fbmFuZGNfaXNfbGFzdF9jdyhlY2MsIGkpICYmICFob3N0LT5jb2Rld29y ZF9maXh1cCkgewo+ICAJCQlkYXRhX3NpemUgPSBlY2MtPnNpemUgLSAoKGVjYy0+c3RlcHMgLSAx KSA8PCAyKTsKPiAgCQkJb29iX3NpemUgPSAoZWNjLT5zdGVwcyA8PCAyKSArIGhvc3QtPmVjY19i eXRlc19odyArCj4gIAkJCQkgICBob3N0LT5zcGFyZV9ieXRlczsKPiBAQCAtMjAzNyw2ICsyMDY2 LDU1IEBAIHN0YXRpYyBpbnQgY29weV9sYXN0X2N3KHN0cnVjdCBxY29tX25hbmRfaG9zdCAqaG9z dCwgaW50IHBhZ2UpCj4gIAlyZXR1cm4gcmV0Owo+ICB9Cj4gIAo+ICtzdGF0aWMgYm9vbAo+ICtx Y29tX25hbmRjX2lzX2Jvb3RfcGFnZShzdHJ1Y3QgcWNvbV9uYW5kX2hvc3QgKmhvc3QsIGludCBw YWdlKQoKTW92ZSBmdW5jdGlvbiBuYW1lIHRvIHByZXZpb3VzIGxpbmUuIElmIGl0IGV4Y2VlZHMg MTAwIGxpbmVzIHRoZW4gd3JhcAphcmd1bWVudHMuCgpzL3Fjb21fbmFuZGNfaXNfYm9vdF9wYWdl L3Fjb21fbmFuZGNfaXNfYm9vdF9wYXJ0aXRpb24KCj4gK3sKPiArCXN0cnVjdCBxY29tX25hbmRf Ym9vdF9wYXJ0aXRpb24gKmJvb3RfcGFydGl0aW9uOwo+ICsJdTMyIHN0YXJ0LCBlbmQ7Cj4gKwlp bnQgaTsKPiArCj4gKwlmb3IgKGkgPSAwOyBpIDwgaG9zdC0+bnJfYm9vdF9wYXJ0aXRpb25zOyBp KyspIHsKPiArCQlib290X3BhcnRpdGlvbiA9ICZob3N0LT5ib290X3BhcnRpdGlvbnNbaV07Cj4g KwkJc3RhcnQgPSBib290X3BhcnRpdGlvbi0+cGFnZV9vZmZzZXQ7Cj4gKwkJZW5kID0gc3RhcnQg KyBib290X3BhcnRpdGlvbi0+cGFnZV9zaXplOwo+ICsKPiArCQkvKiBCb290IHBhZ2VzIGFyZSBu b3JtYWxseSBhdCB0aGUgc3RhcnQgb2YKCkJsb2NrIGNvbW1lbnRzIHNob3VsZCBzdGFydCB3aXRo OgoKCS8qCgkgKiAuLi4KCkFsc28sIGFyZSB5b3Ugc3VyZSB0aGF0IG9ubHkgZmV3IHBhZ2VzIGlu IHRoZSBwYXJ0aXRpb25zIGhhdmUgZGlmZmVyZW50IGxheW91dAphbmQgbm90IGFsbCBwYWdlcz8g SWYgbm90LCB0aGVuIHRoaXMgY29tbWVudCBuZWVkcyB0byBiZSByZXdvcmRlZC4KCj4gKwkJICog dGhlIG5hbmQgaW4gdmFyaW91cyBwYXJ0aXRpb24uCj4gKwkJICogQ2hlY2sgdGhlIHBhZ2UgZnJv bSB0aGUgYm9vdCBwYWdlIGVuZCBmaXJzdAo+ICsJCSAqIHRvIHNhdmUgb25lIGV4dHJhIGNoZWNr IGFuZCBvcHRpbWl6ZSB0aGlzCj4gKwkJICogaW4gY2FzZSByZWFsIG5vLWJvb3QgcGFydGl0aW9u IGFyZSB1c2VkLgo+ICsJCSAqLwo+ICsJCWlmIChwYWdlIDwgZW5kICYmIHBhZ2UgPj0gc3RhcnQp Cj4gKwkJCXJldHVybiB0cnVlOwo+ICsJfQo+ICsKPiArCXJldHVybiBmYWxzZTsKPiArfQo+ICsK PiArc3RhdGljIHZvaWQKPiArcWNvbV9uYW5kY19jb2Rld29yZF9maXh1cChzdHJ1Y3QgcWNvbV9u YW5kX2hvc3QgKmhvc3QsIGludCBwYWdlKQo+ICt7Cj4gKwlib29sIGNvZGV3b3JkX2ZpeHVwID0g cWNvbV9uYW5kY19pc19ib290X3BhZ2UoaG9zdCwgcGFnZSk7Cj4gKwo+ICsJLyogU2tpcCBjb25m IHdyaXRlIGlmIHdlIGFyZSBhbHJlYWR5IGluIHRoZSBjb3JyZWN0IG1vZGUgKi8KPiArCWlmIChj b2Rld29yZF9maXh1cCA9PSBob3N0LT5jb2Rld29yZF9maXh1cCkKPiArCQlyZXR1cm47Cj4gKwo+ ICsJaG9zdC0+Y29kZXdvcmRfZml4dXAgPSBjb2Rld29yZF9maXh1cDsKPiArCj4gKwlob3N0LT5j d19kYXRhID0gY29kZXdvcmRfZml4dXAgPyA1MTIgOiA1MTY7Cj4gKwlob3N0LT5zcGFyZV9ieXRl cyA9IGhvc3QtPmN3X3NpemUgLSBob3N0LT5lY2NfYnl0ZXNfaHcgLQo+ICsJCQkgICAgaG9zdC0+ YmJtX3NpemUgLSBob3N0LT5jd19kYXRhOwo+ICsKPiArCWhvc3QtPmNmZzAgJj0gfihTUEFSRV9T SVpFX0JZVEVTX01BU0sgfCBVRF9TSVpFX0JZVEVTX01BU0spOwo+ICsJaG9zdC0+Y2ZnMCB8PSBo b3N0LT5zcGFyZV9ieXRlcyA8PCBTUEFSRV9TSVpFX0JZVEVTIHwKPiArCQkgICAgICBob3N0LT5j d19kYXRhIDw8IFVEX1NJWkVfQllURVM7Cj4gKwo+ICsJaG9zdC0+ZWNjX2JjaF9jZmcgJj0gfkVD Q19OVU1fREFUQV9CWVRFU19NQVNLOwo+ICsJaG9zdC0+ZWNjX2JjaF9jZmcgfD0gaG9zdC0+Y3df ZGF0YSA8PCBFQ0NfTlVNX0RBVEFfQllURVM7Cj4gKwlob3N0LT5lY2NfYnVmX2NmZyA9IChjb2Rl d29yZF9maXh1cCA/IDB4MWZmIDogMHgyMDMpIDw8IE5VTV9TVEVQUzsKCnMvMWZmLyg1MTIgLSAx KQpzLzIwMy8oNTE2IC0gMSkKCj4gK30KPiArCj4gIC8qIGltcGxlbWVudHMgZWNjLT5yZWFkX3Bh Z2UoKSAqLwo+ICBzdGF0aWMgaW50IHFjb21fbmFuZGNfcmVhZF9wYWdlKHN0cnVjdCBuYW5kX2No aXAgKmNoaXAsIHVpbnQ4X3QgKmJ1ZiwKPiAgCQkJCWludCBvb2JfcmVxdWlyZWQsIGludCBwYWdl KQo+IEBAIC0yMDQ1LDYgKzIxMjMsOSBAQCBzdGF0aWMgaW50IHFjb21fbmFuZGNfcmVhZF9wYWdl KHN0cnVjdCBuYW5kX2NoaXAgKmNoaXAsIHVpbnQ4X3QgKmJ1ZiwKPiAgCXN0cnVjdCBxY29tX25h bmRfY29udHJvbGxlciAqbmFuZGMgPSBnZXRfcWNvbV9uYW5kX2NvbnRyb2xsZXIoY2hpcCk7Cj4g IAl1OCAqZGF0YV9idWYsICpvb2JfYnVmID0gTlVMTDsKPiAgCj4gKwlpZiAoaG9zdC0+bnJfYm9v dF9wYXJ0aXRpb25zKQo+ICsJCXFjb21fbmFuZGNfY29kZXdvcmRfZml4dXAoaG9zdCwgcGFnZSk7 Cj4gKwo+ICAJbmFuZF9yZWFkX3BhZ2Vfb3AoY2hpcCwgcGFnZSwgMCwgTlVMTCwgMCk7Cj4gIAlk YXRhX2J1ZiA9IGJ1ZjsKPiAgCW9vYl9idWYgPSBvb2JfcmVxdWlyZWQgPyBjaGlwLT5vb2JfcG9p IDogTlVMTDsKPiBAQCAtMjA2NCw2ICsyMTQ1LDkgQEAgc3RhdGljIGludCBxY29tX25hbmRjX3Jl YWRfcGFnZV9yYXcoc3RydWN0IG5hbmRfY2hpcCAqY2hpcCwgdWludDhfdCAqYnVmLAo+ICAJaW50 IGN3LCByZXQ7Cj4gIAl1OCAqZGF0YV9idWYgPSBidWYsICpvb2JfYnVmID0gY2hpcC0+b29iX3Bv aTsKPiAgCj4gKwlpZiAoaG9zdC0+bnJfYm9vdF9wYXJ0aXRpb25zKQo+ICsJCXFjb21fbmFuZGNf Y29kZXdvcmRfZml4dXAoaG9zdCwgcGFnZSk7Cj4gKwo+ICAJZm9yIChjdyA9IDA7IGN3IDwgZWNj LT5zdGVwczsgY3crKykgewo+ICAJCXJldCA9IHFjb21fbmFuZGNfcmVhZF9jd19yYXcobXRkLCBj aGlwLCBkYXRhX2J1Ziwgb29iX2J1ZiwKPiAgCQkJCQkgICAgIHBhZ2UsIGN3KTsKPiBAQCAtMjA4 NCw2ICsyMTY4LDkgQEAgc3RhdGljIGludCBxY29tX25hbmRjX3JlYWRfb29iKHN0cnVjdCBuYW5k X2NoaXAgKmNoaXAsIGludCBwYWdlKQo+ICAJc3RydWN0IHFjb21fbmFuZF9jb250cm9sbGVyICpu YW5kYyA9IGdldF9xY29tX25hbmRfY29udHJvbGxlcihjaGlwKTsKPiAgCXN0cnVjdCBuYW5kX2Vj Y19jdHJsICplY2MgPSAmY2hpcC0+ZWNjOwo+ICAKPiArCWlmIChob3N0LT5ucl9ib290X3BhcnRp dGlvbnMpCj4gKwkJcWNvbV9uYW5kY19jb2Rld29yZF9maXh1cChob3N0LCBwYWdlKTsKPiArCj4g IAljbGVhcl9yZWFkX3JlZ3MobmFuZGMpOwo+ICAJY2xlYXJfYmFtX3RyYW5zYWN0aW9uKG5hbmRj KTsKPiAgCj4gQEAgLTIxMDQsNiArMjE5MSw5IEBAIHN0YXRpYyBpbnQgcWNvbV9uYW5kY193cml0 ZV9wYWdlKHN0cnVjdCBuYW5kX2NoaXAgKmNoaXAsIGNvbnN0IHVpbnQ4X3QgKmJ1ZiwKPiAgCXU4 ICpkYXRhX2J1ZiwgKm9vYl9idWY7Cj4gIAlpbnQgaSwgcmV0Owo+ICAKPiArCWlmIChob3N0LT5u cl9ib290X3BhcnRpdGlvbnMpCj4gKwkJcWNvbV9uYW5kY19jb2Rld29yZF9maXh1cChob3N0LCBw YWdlKTsKPiArCj4gIAluYW5kX3Byb2dfcGFnZV9iZWdpbl9vcChjaGlwLCBwYWdlLCAwLCBOVUxM LCAwKTsKPiAgCj4gIAljbGVhcl9yZWFkX3JlZ3MobmFuZGMpOwo+IEBAIC0yMTE5LDcgKzIyMDks NyBAQCBzdGF0aWMgaW50IHFjb21fbmFuZGNfd3JpdGVfcGFnZShzdHJ1Y3QgbmFuZF9jaGlwICpj aGlwLCBjb25zdCB1aW50OF90ICpidWYsCj4gIAlmb3IgKGkgPSAwOyBpIDwgZWNjLT5zdGVwczsg aSsrKSB7Cj4gIAkJaW50IGRhdGFfc2l6ZSwgb29iX3NpemU7Cj4gIAo+IC0JCWlmIChxY29tX25h bmRjX2lzX2xhc3RfY3coZWNjLCBpKSkgewo+ICsJCWlmIChxY29tX25hbmRjX2lzX2xhc3RfY3co ZWNjLCBpKSAmJiAhaG9zdC0+Y29kZXdvcmRfZml4dXApIHsKPiAgCQkJZGF0YV9zaXplID0gZWNj LT5zaXplIC0gKChlY2MtPnN0ZXBzIC0gMSkgPDwgMik7Cj4gIAkJCW9vYl9zaXplID0gKGVjYy0+ c3RlcHMgPDwgMikgKyBob3N0LT5lY2NfYnl0ZXNfaHcgKwo+ICAJCQkJICAgaG9zdC0+c3BhcmVf Ynl0ZXM7Cj4gQEAgLTIxNzYsNiArMjI2Niw5IEBAIHN0YXRpYyBpbnQgcWNvbV9uYW5kY193cml0 ZV9wYWdlX3JhdyhzdHJ1Y3QgbmFuZF9jaGlwICpjaGlwLAo+ICAJdTggKmRhdGFfYnVmLCAqb29i X2J1ZjsKPiAgCWludCBpLCByZXQ7Cj4gIAo+ICsJaWYgKGhvc3QtPm5yX2Jvb3RfcGFydGl0aW9u cykKPiArCQlxY29tX25hbmRjX2NvZGV3b3JkX2ZpeHVwKGhvc3QsIHBhZ2UpOwo+ICsKPiAgCW5h bmRfcHJvZ19wYWdlX2JlZ2luX29wKGNoaXAsIHBhZ2UsIDAsIE5VTEwsIDApOwo+ICAJY2xlYXJf cmVhZF9yZWdzKG5hbmRjKTsKPiAgCWNsZWFyX2JhbV90cmFuc2FjdGlvbihuYW5kYyk7Cj4gQEAg LTIxOTQsNyArMjI4Nyw3IEBAIHN0YXRpYyBpbnQgcWNvbV9uYW5kY193cml0ZV9wYWdlX3Jhdyhz dHJ1Y3QgbmFuZF9jaGlwICpjaGlwLAo+ICAJCWRhdGFfc2l6ZTEgPSBtdGQtPndyaXRlc2l6ZSAt IGhvc3QtPmN3X3NpemUgKiAoZWNjLT5zdGVwcyAtIDEpOwo+ICAJCW9vYl9zaXplMSA9IGhvc3Qt PmJibV9zaXplOwo+ICAKPiAtCQlpZiAocWNvbV9uYW5kY19pc19sYXN0X2N3KGVjYywgaSkpIHsK PiArCQlpZiAocWNvbV9uYW5kY19pc19sYXN0X2N3KGVjYywgaSkgJiYgIWhvc3QtPmNvZGV3b3Jk X2ZpeHVwKSB7Cj4gIAkJCWRhdGFfc2l6ZTIgPSBlY2MtPnNpemUgLSBkYXRhX3NpemUxIC0KPiAg CQkJCSAgICAgKChlY2MtPnN0ZXBzIC0gMSkgPDwgMik7Cj4gIAkJCW9vYl9zaXplMiA9IChlY2Mt PnN0ZXBzIDw8IDIpICsgaG9zdC0+ZWNjX2J5dGVzX2h3ICsKPiBAQCAtMjI1NCw2ICsyMzQ3LDkg QEAgc3RhdGljIGludCBxY29tX25hbmRjX3dyaXRlX29vYihzdHJ1Y3QgbmFuZF9jaGlwICpjaGlw LCBpbnQgcGFnZSkKPiAgCWludCBkYXRhX3NpemUsIG9vYl9zaXplOwo+ICAJaW50IHJldDsKPiAg Cj4gKwlpZiAoaG9zdC0+bnJfYm9vdF9wYXJ0aXRpb25zKQo+ICsJCXFjb21fbmFuZGNfY29kZXdv cmRfZml4dXAoaG9zdCwgcGFnZSk7Cj4gKwo+ICAJaG9zdC0+dXNlX2VjYyA9IHRydWU7Cj4gIAlj bGVhcl9iYW1fdHJhbnNhY3Rpb24obmFuZGMpOwo+ICAKPiBAQCAtMjkwMiw2ICsyOTk4LDcxIEBA IHN0YXRpYyBpbnQgcWNvbV9uYW5kY19zZXR1cChzdHJ1Y3QgcWNvbV9uYW5kX2NvbnRyb2xsZXIg Km5hbmRjKQo+ICAKPiAgc3RhdGljIGNvbnN0IGNoYXIgKiBjb25zdCBwcm9iZXNbXSA9IHsgImNt ZGxpbmVwYXJ0IiwgIm9mcGFydCIsICJxY29tc21lbSIsIE5VTEwgfTsKPiAgCj4gK3N0YXRpYyBp bnQgcWNvbV9uYW5kX2hvc3RfcGFyc2VfYm9vdF9wYXJ0aXRpb25zKHN0cnVjdCBxY29tX25hbmRf Y29udHJvbGxlciAqbmFuZGMsCj4gKwkJCQkJCXN0cnVjdCBxY29tX25hbmRfaG9zdCAqaG9zdCwK PiArCQkJCQkJc3RydWN0IGRldmljZV9ub2RlICpkbikKPiArewo+ICsJc3RydWN0IG5hbmRfY2hp cCAqY2hpcCA9ICZob3N0LT5jaGlwOwo+ICsJc3RydWN0IG10ZF9pbmZvICptdGQgPSBuYW5kX3Rv X210ZChjaGlwKTsKPiArCXN0cnVjdCBxY29tX25hbmRfYm9vdF9wYXJ0aXRpb24gKmJvb3RfcGFy dGl0aW9uOwo+ICsJc3RydWN0IGRldmljZSAqZGV2ID0gbmFuZGMtPmRldjsKPiArCWludCBwYXJ0 aXRpb25zX2NvdW50LCBpLCBqLCByZXQ7Cj4gKwo+ICsJaWYgKCFuYW5kYy0+cHJvcHMtPnVzZV9j b2Rld29yZF9maXh1cCkKPiArCQlyZXR1cm4gMDsKCk1vdmUgdGhpcyBjaGVjayB0byBjYWxsZXIg YXMgSSBzdWdnZXN0ZWQgcHJldmlvdXNseS4KCj4gKwo+ICsJaWYgKCFvZl9maW5kX3Byb3BlcnR5 KGRuLCAicWNvbSxib290LXBhcnRpdGlvbnMiLCBOVUxMKSkKPiArCQlyZXR1cm4gMDsKPiArCj4g KwlwYXJ0aXRpb25zX2NvdW50ID0gb2ZfcHJvcGVydHlfY291bnRfdTMyX2VsZW1zKGRuLCAicWNv bSxib290LXBhcnRpdGlvbnMiKTsKPiArCWlmIChwYXJ0aXRpb25zX2NvdW50IDwgMCkgewoKcGFy dGl0aW9uc19jb3VudCA8PSAwCgo+ICsJCWRldl9lcnIoZGV2LCAiRXJyb3IgcGFyc2luZyBib290 IHBhcnRpdGlvbi4iKTsKCkFkZCBuZXdsaW5lIGF0IHRoZSBlbmQgb2YgZXJyb3IgbWVzc2FnZQoK PiArCQlyZXR1cm4gcmV0Owo+ICsJfQo+ICsKPiArCWhvc3QtPm5yX2Jvb3RfcGFydGl0aW9ucyA9 IHBhcnRpdGlvbnNfY291bnQgLyAyOwo+ICsJaG9zdC0+Ym9vdF9wYXJ0aXRpb25zID0gZGV2bV9r Y2FsbG9jKGRldiwgaG9zdC0+bnJfYm9vdF9wYXJ0aXRpb25zLAo+ICsJCQkJCSAgICAgc2l6ZW9m KCpob3N0LT5ib290X3BhcnRpdGlvbnMpLCBHRlBfS0VSTkVMKTsKPiArCWlmICghaG9zdC0+Ym9v dF9wYXJ0aXRpb25zKQoKaG9zdC0+bnJfYm9vdF9wYXJ0aXRpb25zID0gMDsKCj4gKwkJcmV0dXJu IC1FTk9NRU07Cj4gKwo+ICsJZm9yIChpID0gMCwgaiA9IDA7IGkgPCBob3N0LT5ucl9ib290X3Bh cnRpdGlvbnM7IGkrKywgaiArPSAyKSB7Cj4gKwkJYm9vdF9wYXJ0aXRpb24gPSAmaG9zdC0+Ym9v dF9wYXJ0aXRpb25zW2ldOwo+ICsKPiArCQlyZXQgPSBvZl9wcm9wZXJ0eV9yZWFkX3UzMl9pbmRl eChkbiwgInFjb20sYm9vdC1wYXJ0aXRpb25zIiwgaiwKPiArCQkJCQkJICZib290X3BhcnRpdGlv bi0+cGFnZV9vZmZzZXQpOwo+ICsJCWlmIChyZXQpIHsKPiArCQkJZGV2X2VycihkZXYsICJFcnJv ciBwYXJzaW5nIGJvb3QgcGFydGl0aW9uIG9mZnNldCBhdCBpbmRleCAlZCIsIGkpOwoKQWRkIG5l d2xpbmUgYXQgdGhlIGVuZCBvZiBlcnJvciBtZXNzYWdlLiBEbyB0aGUgc2FtZSBmb3IgYWxsIGVy cm9yIHByaW50cy4KCj4gKwkJCXJldHVybiByZXQ7Cj4gKwkJfQo+ICsKPiArCQlpZiAoYm9vdF9w YXJ0aXRpb24tPnBhZ2Vfb2Zmc2V0ICUgbXRkLT53cml0ZXNpemUpIHsKPiArCQkJZGV2X2Vycihk ZXYsICJCb290IHBhcnRpdGlvbiBvZmZzZXQgbm90IG11bHRpcGxlIG9mIHdyaXRlc2l6ZSBhdCBp bmRleCAlaSIsCj4gKwkJCQlpKTsKPiArCQkJcmV0dXJuIC1FSU5WQUw7Cj4gKwkJfQo+ICsJCS8q IENvbnZlcnQgb2Zmc2V0IHRvIG5hbmQgcGFnZXMgKi8KCnMvcGFnZXMvcGFydGl0aW9ucwoKPiAr CQlib290X3BhcnRpdGlvbi0+cGFnZV9vZmZzZXQgLz0gbXRkLT53cml0ZXNpemU7CgpzL3BhZ2Vf b2Zmc2V0L29mZnNldAoKPiArCj4gKwkJcmV0ID0gb2ZfcHJvcGVydHlfcmVhZF91MzJfaW5kZXgo ZG4sICJxY29tLGJvb3QtcGFydGl0aW9ucyIsIGogKyAxLAo+ICsJCQkJCQkgJmJvb3RfcGFydGl0 aW9uLT5wYWdlX3NpemUpOwo+ICsJCWlmIChyZXQpIHsKPiArCQkJZGV2X2VycihkZXYsICJFcnJv ciBwYXJzaW5nIGJvb3QgcGFydGl0aW9uIHNpemUgYXQgaW5kZXggJWQiLCBpKTsKPiArCQkJcmV0 dXJuIHJldDsKPiArCQl9Cj4gKwo+ICsJCWlmIChib290X3BhcnRpdGlvbi0+cGFnZV9zaXplICUg bXRkLT53cml0ZXNpemUpIHsKCnMvcGFnZV9zaXplL3NpemUgaGVyZSBhbmQgYmVsb3cKCj4gKwkJ CWRldl9lcnIoZGV2LCAiQm9vdCBwYXJ0aXRpb24gc2l6ZSBub3QgbXVsdGlwbGUgb2Ygd3JpdGVz aXplIGF0IGluZGV4ICVpIiwKPiArCQkJCWkpOwo+ICsJCQlyZXR1cm4gLUVJTlZBTDsKPiArCQl9 Cj4gKwkJLyogQ29udmVydCBzaXplIHRvIG5hbmQgcGFnZXMgKi8KCnMvcGFnZXMvcGFydGl0aW9u cwoKVGhhbmtzLApNYW5pCgo+ICsJCWJvb3RfcGFydGl0aW9uLT5wYWdlX3NpemUgLz0gbXRkLT53 cml0ZXNpemU7Cj4gKwl9Cj4gKwo+ICsJcmV0dXJuIDA7Cj4gK30KPiArCj4gIHN0YXRpYyBpbnQg cWNvbV9uYW5kX2hvc3RfaW5pdF9hbmRfcmVnaXN0ZXIoc3RydWN0IHFjb21fbmFuZF9jb250cm9s bGVyICpuYW5kYywKPiAgCQkJCQkgICAgc3RydWN0IHFjb21fbmFuZF9ob3N0ICpob3N0LAo+ICAJ CQkJCSAgICBzdHJ1Y3QgZGV2aWNlX25vZGUgKmRuKQo+IEBAIC0yOTcwLDYgKzMxMzEsOCBAQCBz dGF0aWMgaW50IHFjb21fbmFuZF9ob3N0X2luaXRfYW5kX3JlZ2lzdGVyKHN0cnVjdCBxY29tX25h bmRfY29udHJvbGxlciAqbmFuZGMsCj4gIAlpZiAocmV0KQo+ICAJCW5hbmRfY2xlYW51cChjaGlw KTsKPiAgCj4gKwlxY29tX25hbmRfaG9zdF9wYXJzZV9ib290X3BhcnRpdGlvbnMobmFuZGMsIGhv c3QsIGRuKTsKPiArCj4gIAlyZXR1cm4gcmV0Owo+ICB9Cj4gIAo+IEBAIC0zMTM1LDYgKzMyOTgs NyBAQCBzdGF0aWMgaW50IHFjb21fbmFuZGNfcmVtb3ZlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2Ug KnBkZXYpCj4gIHN0YXRpYyBjb25zdCBzdHJ1Y3QgcWNvbV9uYW5kY19wcm9wcyBpcHE4MDZ4X25h bmRjX3Byb3BzID0gewo+ICAJLmVjY19tb2RlcyA9IChFQ0NfUlNfNEJJVCB8IEVDQ19CQ0hfOEJJ VCksCj4gIAkuaXNfYmFtID0gZmFsc2UsCj4gKwkudXNlX2NvZGV3b3JkX2ZpeHVwID0gdHJ1ZSwK PiAgCS5kZXZfY21kX3JlZ19zdGFydCA9IDB4MCwKPiAgfTsKPiAgCj4gLS0gCj4gMi4zNi4xCj4g CgotLSAK4K6u4K6j4K6/4K614K6j4K+N4K6j4K6p4K+NIOCumuCupOCuvuCumuCuv+CuteCuruCv jQoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f CkxpbnV4IE1URCBkaXNjdXNzaW9uIG1haWxpbmcgbGlzdApodHRwOi8vbGlzdHMuaW5mcmFkZWFk Lm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LW10ZC8K