From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CF6BCCA47E for ; Thu, 9 Jun 2022 17:12:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234580AbiFIRL7 (ORCPT ); Thu, 9 Jun 2022 13:11:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230002AbiFIRL6 (ORCPT ); Thu, 9 Jun 2022 13:11:58 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F41C206121; Thu, 9 Jun 2022 10:11:56 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id E357CB82BCD; Thu, 9 Jun 2022 17:11:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 668A0C34114; Thu, 9 Jun 2022 17:11:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1654794713; bh=0baujAxOxtu9nlFlWgA3ofK6gmRM2jyD7B9ffXWaQzU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=IP9Z8uZm4QXHgp51TChdd+OsPx4GO5svd/avqg97vDQdbytSCDg3iOvSEDvdsptM2 9ji/3JLFftOdq5RS9yh+5paknZpTyV0K+aGbB7u1LhHVqDZhdgxuPyXMVB+EtjNJkM rSmOI/e1/TYCWgvz+2yvnn4jEhT512jMuTnv73xeXwXuf3wUt6sV66GVfNME5zJug2 RY7lc5vjRF7EKO6x/qQ6J+AcMj69fJ53v+44hHXfxy0ppaT6M2IsDMU5ZYKichms0s CSlgoJ0AYJWWG1EaMi4IBj5kuCuMVRhUZ/cX2vLmCtWo2f2B+sCi1kY3nKS/VogMDc /AfRdtiW58jZw== Date: Thu, 9 Jun 2022 22:41:41 +0530 From: Manivannan Sadhasivam To: Ansuel Smith Cc: Andy Gross , Bjorn Andersson , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 2/3] mtd: nand: raw: qcom_nandc: add support for unprotected spare data pages Message-ID: <20220609171141.GB5081@thinkpad> References: <20220609132344.17548-1-ansuelsmth@gmail.com> <20220609132344.17548-3-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220609132344.17548-3-ansuelsmth@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Thu, Jun 09, 2022 at 03:23:43PM +0200, Ansuel Smith wrote: > IPQ8064 nand have special pages where a different layout scheme is used. > These special page are used by boot partition and on reading them > lots of warning are reported about wrong ECC data and if written to > results in broken data and not bootable device. > > The layout scheme used by these special page consist in using 512 bytes > as the codeword size (even for the last codeword) while writing to CFG0 > register. This forces the NAND controller to unprotect the 4 bytes of > spare data. > > Since the kernel is unaware of this different layout for these special > page, it does try to protect the spare data too during read/write and > warn about CRC errors. > > Add support for this by permitting the user to declare these special > pages in dts by declaring offset and size of the partition. The driver > internally will convert these value to nand pages. > > On user read/write the page is checked and if it's a boot page the > correct layout is used. > > Signed-off-by: Ansuel Smith > --- > drivers/mtd/nand/raw/qcom_nandc.c | 204 +++++++++++++++++++++++++++++- > 1 file changed, 199 insertions(+), 5 deletions(-) > > diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c > index 7fbbd3e7784c..29a16534bee3 100644 > --- a/drivers/mtd/nand/raw/qcom_nandc.c > +++ b/drivers/mtd/nand/raw/qcom_nandc.c > @@ -80,8 +80,10 @@ > #define DISABLE_STATUS_AFTER_WRITE 4 > #define CW_PER_PAGE 6 > #define UD_SIZE_BYTES 9 > +#define UD_SIZE_BYTES_MASK GENMASK(18, 9) > #define ECC_PARITY_SIZE_BYTES_RS 19 > #define SPARE_SIZE_BYTES 23 > +#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23) > #define NUM_ADDR_CYCLES 27 > #define STATUS_BFR_READ 30 > #define SET_RD_MODE_AFTER_STATUS 31 > @@ -102,6 +104,7 @@ > #define ECC_MODE 4 > #define ECC_PARITY_SIZE_BYTES_BCH 8 > #define ECC_NUM_DATA_BYTES 16 > +#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16) > #define ECC_FORCE_CLK_OPEN 30 > > /* NAND_DEV_CMD1 bits */ > @@ -418,6 +421,19 @@ struct qcom_nand_controller { > const struct qcom_nandc_props *props; > }; > > +/* > + * NAND special boot partitions > + * > + * @page_offset: offset of the partition where spare data is not protected > + * by ECC (value in pages) > + * @page_offset: size of the partition where spare data is not protected > + * by ECC (value in pages) > + */ > +struct qcom_nand_boot_partition { > + u32 page_offset; > + u32 page_size; > +}; > + > /* > * NAND chip structure > * > @@ -434,6 +450,8 @@ struct qcom_nand_controller { > * @ecc_bytes_hw: ECC bytes used by controller hardware for this > * chip > * > + * @codeword_fixup: keep track of the current layout used by > + * the driver for read/write operation. > * @use_ecc: request the controller to use ECC for the > * upcoming read/write > * @bch_enabled: flag to tell whether BCH ECC mode is used > @@ -445,6 +463,11 @@ struct qcom_nand_controller { > * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for > * ecc/non-ecc mode for the current nand flash > * device > + * > + * @nr_boot_partitions: count of the boot partitions where spare data is not > + * protected by ECC > + * @boot_partitions: array of boot partitions where offset and size of the > + * boot partitions are stored > */ > struct qcom_nand_host { > struct nand_chip chip; > @@ -457,6 +480,7 @@ struct qcom_nand_host { > int spare_bytes; > int bbm_size; > > + bool codeword_fixup; > bool use_ecc; > bool bch_enabled; > u8 status; > @@ -468,6 +492,9 @@ struct qcom_nand_host { > u32 ecc_bch_cfg; > u32 clrflashstatus; > u32 clrreadstatus; > + > + int nr_boot_partitions; > + struct qcom_nand_boot_partition *boot_partitions; > }; > > /* > @@ -477,6 +504,7 @@ struct qcom_nand_host { > * @is_bam - whether NAND controller is using BAM > * @is_qpic - whether NAND CTRL is part of qpic IP > * @qpic_v2 - flag to indicate QPIC IP version 2 > + * @use_codeword_fixup - whether NAND has different layout for boot partitions > * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset > */ > struct qcom_nandc_props { > @@ -484,6 +512,7 @@ struct qcom_nandc_props { > bool is_bam; > bool is_qpic; > bool qpic_v2; > + bool use_codeword_fixup; > u32 dev_cmd_reg_start; > }; > > @@ -1703,7 +1732,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip, > data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); > oob_size1 = host->bbm_size; > > - if (qcom_nandc_is_last_cw(ecc, cw)) { > + if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { > data_size2 = ecc->size - data_size1 - > ((ecc->steps - 1) * 4); > oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw + > @@ -1784,7 +1813,7 @@ check_for_erased_page(struct qcom_nand_host *host, u8 *data_buf, > } > > for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) { > - if (qcom_nandc_is_last_cw(ecc, cw)) { > + if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { > data_size = ecc->size - ((ecc->steps - 1) * 4); > oob_size = (ecc->steps * 4) + host->ecc_bytes_hw; > } else { > @@ -1942,7 +1971,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf, > for (i = 0; i < ecc->steps; i++) { > int data_size, oob_size; > > - if (qcom_nandc_is_last_cw(ecc, i)) { > + if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { > data_size = ecc->size - ((ecc->steps - 1) << 2); > oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + > host->spare_bytes; > @@ -2039,6 +2068,78 @@ static int copy_last_cw(struct qcom_nand_host *host, int page) > return ret; > } > > +static bool qcom_nandc_is_boot_partition(struct qcom_nand_host *host, int page) > +{ > + struct qcom_nand_boot_partition *boot_partition; > + u32 start, end; > + int i; > + > + /* > + * Since the frequent access will be to the non-boot partitions like rootfs, > + * optimize the page check by: > + > + * 1. Checking if the page lies after the last boot partition. This is not implemented in code. > + * 2. Checking from the boot partition end. > + * I think we can leave the below example part. I just asked to include the actual usecase and above points suffice. > + * This comes from the fact that an example partition table is: > + * mtd0: 00c80000 00020000 "qcadata" (require codeword fix) > + * mtd1: 00500000 00020000 "APPSBL" (require codeword fix) > + * mtd2: 00080000 00020000 "APPSBLENV" (doesn't require codeword fix) > + * mtd3: 00140000 00020000 "art" (doesn't require codeword fix) > + * mtd4: 00140000 00020000 "artbak" (doesn't require codeword fix) > + * mtd5: 00400000 00020000 "kernel" (doesn't require codeword fix) > + * mtd6: 06080000 00020000 "ubi" (doesn't require codeword fix) > + * mtd7: 00700000 00020000 "reserve" (doesn't require codeword fix) > + * > + * where the boot partition are always the first partition and rootfs > + * partition are at the end. > + * > + * Defining a big single boot partition is not possible since some > + * device have the following partition table: > + * mtd0: 00c80000 00020000 "qcadata" (require codeword fix) > + * mtd1: 00500000 00020000 "APPSBL" (require codeword fix) > + * mtd2: 00080000 00020000 "APPSBLENV" (doesn't require codeword fix) > + * mtd3: 00140000 00020000 "APPSBL2" (require codeword fix) > + * > + * where a backup partition is placed after a partition where the > + * codeword fix should not be used. > + */ > + for (i = host->nr_boot_partitions - 1; i >= 0; i--) { > + boot_partition = &host->boot_partitions[i]; > + start = boot_partition->page_offset; > + end = start + boot_partition->page_size; > + > + if (page < end && page >= start) > + return true; > + } > + > + return false; > +} > + > +static void > +qcom_nandc_codeword_fixup(struct qcom_nand_host *host, int page) > +{ > + bool codeword_fixup = qcom_nandc_is_boot_partition(host, page); > + > + /* Skip conf write if we are already in the correct mode */ > + if (codeword_fixup == host->codeword_fixup) > + return; > + > + host->codeword_fixup = codeword_fixup; > + > + host->cw_data = codeword_fixup ? 512 : 516; > + host->spare_bytes = host->cw_size - host->ecc_bytes_hw - > + host->bbm_size - host->cw_data; > + > + host->cfg0 &= ~(SPARE_SIZE_BYTES_MASK | UD_SIZE_BYTES_MASK); > + host->cfg0 |= host->spare_bytes << SPARE_SIZE_BYTES | > + host->cw_data << UD_SIZE_BYTES; > + > + host->ecc_bch_cfg &= ~ECC_NUM_DATA_BYTES_MASK; > + host->ecc_bch_cfg |= host->cw_data << ECC_NUM_DATA_BYTES; > + host->ecc_buf_cfg = (host->cw_data - 1) << NUM_STEPS; > +} > + > /* implements ecc->read_page() */ > static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf, > int oob_required, int page) > @@ -2047,6 +2148,9 @@ static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf, > struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); > u8 *data_buf, *oob_buf = NULL; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > nand_read_page_op(chip, page, 0, NULL, 0); > data_buf = buf; > oob_buf = oob_required ? chip->oob_poi : NULL; > @@ -2066,6 +2170,9 @@ static int qcom_nandc_read_page_raw(struct nand_chip *chip, uint8_t *buf, > int cw, ret; > u8 *data_buf = buf, *oob_buf = chip->oob_poi; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > for (cw = 0; cw < ecc->steps; cw++) { > ret = qcom_nandc_read_cw_raw(mtd, chip, data_buf, oob_buf, > page, cw); > @@ -2086,6 +2193,9 @@ static int qcom_nandc_read_oob(struct nand_chip *chip, int page) > struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); > struct nand_ecc_ctrl *ecc = &chip->ecc; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > clear_read_regs(nandc); > clear_bam_transaction(nandc); > > @@ -2106,6 +2216,9 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const uint8_t *buf, > u8 *data_buf, *oob_buf; > int i, ret; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > nand_prog_page_begin_op(chip, page, 0, NULL, 0); > > clear_read_regs(nandc); > @@ -2121,7 +2234,7 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const uint8_t *buf, > for (i = 0; i < ecc->steps; i++) { > int data_size, oob_size; > > - if (qcom_nandc_is_last_cw(ecc, i)) { > + if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { > data_size = ecc->size - ((ecc->steps - 1) << 2); > oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + > host->spare_bytes; > @@ -2178,6 +2291,9 @@ static int qcom_nandc_write_page_raw(struct nand_chip *chip, > u8 *data_buf, *oob_buf; > int i, ret; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > nand_prog_page_begin_op(chip, page, 0, NULL, 0); > clear_read_regs(nandc); > clear_bam_transaction(nandc); > @@ -2196,7 +2312,7 @@ static int qcom_nandc_write_page_raw(struct nand_chip *chip, > data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); > oob_size1 = host->bbm_size; > > - if (qcom_nandc_is_last_cw(ecc, i)) { > + if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { > data_size2 = ecc->size - data_size1 - > ((ecc->steps - 1) << 2); > oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + > @@ -2256,6 +2372,9 @@ static int qcom_nandc_write_oob(struct nand_chip *chip, int page) > int data_size, oob_size; > int ret; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > host->use_ecc = true; > clear_bam_transaction(nandc); > > @@ -2904,6 +3023,74 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc) > > static const char * const probes[] = { "cmdlinepart", "ofpart", "qcomsmem", NULL }; > > +static int qcom_nand_host_parse_boot_partitions(struct qcom_nand_controller *nandc, > + struct qcom_nand_host *host, > + struct device_node *dn) > +{ > + struct nand_chip *chip = &host->chip; > + struct mtd_info *mtd = nand_to_mtd(chip); > + struct qcom_nand_boot_partition *boot_partition; > + struct device *dev = nandc->dev; > + int partitions_count, i, j, ret; > + > + if (!of_find_property(dn, "qcom,boot-partitions", NULL)) > + return 0; > + > + partitions_count = of_property_count_u32_elems(dn, "qcom,boot-partitions"); > + if (partitions_count <= 0) { > + dev_err(dev, "Error parsing boot partition\n"); > + return ret; > + } > + > + host->nr_boot_partitions = partitions_count / 2; > + host->boot_partitions = devm_kcalloc(dev, host->nr_boot_partitions, > + sizeof(*host->boot_partitions), GFP_KERNEL); > + if (!host->boot_partitions) { > + host->nr_boot_partitions = 0; > + return -ENOMEM; > + } > + > + for (i = 0, j = 0; i < host->nr_boot_partitions; i++, j += 2) { > + boot_partition = &host->boot_partitions[i]; > + > + ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j, > + &boot_partition->page_offset); > + if (ret) { > + dev_err(dev, "Error parsing boot partition offset at index %d", i); Err... You missed adding newline here and below. > + host->nr_boot_partitions = 0; > + return ret; > + } > + > + if (boot_partition->page_offset % mtd->writesize) { > + dev_err(dev, "Boot partition offset not multiple of writesize at index %i\n", > + i); > + host->nr_boot_partitions = 0; > + return -EINVAL; > + } > + /* Convert offset to nand pages */ > + boot_partition->page_offset /= mtd->writesize; > + > + ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j + 1, > + &boot_partition->page_size); > + if (ret) { > + dev_err(dev, "Error parsing boot partition size at index %d\n", i); > + host->nr_boot_partitions = 0; > + return ret; > + } > + > + if (boot_partition->page_size % mtd->writesize) { > + dev_err(dev, "Boot partition size not multiple of writesize at index %i", > + i); > + host->nr_boot_partitions = 0; > + return -EINVAL; > + } > + /* Convert size to nand pages */ > + boot_partition->page_size /= mtd->writesize; > + } > + > + return 0; > +} > + > static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, > struct qcom_nand_host *host, > struct device_node *dn) > @@ -2972,6 +3159,12 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, > if (ret) > nand_cleanup(chip); > > + if (nandc->props->use_codeword_fixup) { > + ret = qcom_nand_host_parse_boot_partitions(nandc, host, dn); > + if (ret) > + return ret; Missed nand_cleanup(). Thanks, Mani > + } > + > return ret; > } > > @@ -3137,6 +3330,7 @@ static int qcom_nandc_remove(struct platform_device *pdev) > static const struct qcom_nandc_props ipq806x_nandc_props = { > .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT), > .is_bam = false, > + .use_codeword_fixup = true, > .dev_cmd_reg_start = 0x0, > }; > > -- > 2.36.1 > -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38667C433EF for ; Thu, 9 Jun 2022 17:28:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: 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List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org T24gVGh1LCBKdW4gMDksIDIwMjIgYXQgMDM6MjM6NDNQTSArMDIwMCwgQW5zdWVsIFNtaXRoIHdy b3RlOgo+IElQUTgwNjQgbmFuZCBoYXZlIHNwZWNpYWwgcGFnZXMgd2hlcmUgYSBkaWZmZXJlbnQg bGF5b3V0IHNjaGVtZSBpcyB1c2VkLgo+IFRoZXNlIHNwZWNpYWwgcGFnZSBhcmUgdXNlZCBieSBi b290IHBhcnRpdGlvbiBhbmQgb24gcmVhZGluZyB0aGVtCj4gbG90cyBvZiB3YXJuaW5nIGFyZSBy ZXBvcnRlZCBhYm91dCB3cm9uZyBFQ0MgZGF0YSBhbmQgaWYgd3JpdHRlbiB0bwo+IHJlc3VsdHMg aW4gYnJva2VuIGRhdGEgYW5kIG5vdCBib290YWJsZSBkZXZpY2UuCj4gCj4gVGhlIGxheW91dCBz Y2hlbWUgdXNlZCBieSB0aGVzZSBzcGVjaWFsIHBhZ2UgY29uc2lzdCBpbiB1c2luZyA1MTIgYnl0 ZXMKPiBhcyB0aGUgY29kZXdvcmQgc2l6ZSAoZXZlbiBmb3IgdGhlIGxhc3QgY29kZXdvcmQpIHdo aWxlIHdyaXRpbmcgdG8gQ0ZHMAo+IHJlZ2lzdGVyLiBUaGlzIGZvcmNlcyB0aGUgTkFORCBjb250 cm9sbGVyIHRvIHVucHJvdGVjdCB0aGUgNCBieXRlcyBvZgo+IHNwYXJlIGRhdGEuCj4gCj4gU2lu Y2UgdGhlIGtlcm5lbCBpcyB1bmF3YXJlIG9mIHRoaXMgZGlmZmVyZW50IGxheW91dCBmb3IgdGhl c2Ugc3BlY2lhbAo+IHBhZ2UsIGl0IGRvZXMgdHJ5IHRvIHByb3RlY3QgdGhlIHNwYXJlIGRhdGEg dG9vIGR1cmluZyByZWFkL3dyaXRlIGFuZAo+IHdhcm4gYWJvdXQgQ1JDIGVycm9ycy4KPiAKPiBB ZGQgc3VwcG9ydCBmb3IgdGhpcyBieSBwZXJtaXR0aW5nIHRoZSB1c2VyIHRvIGRlY2xhcmUgdGhl c2Ugc3BlY2lhbAo+IHBhZ2VzIGluIGR0cyBieSBkZWNsYXJpbmcgb2Zmc2V0IGFuZCBzaXplIG9m IHRoZSBwYXJ0aXRpb24uIFRoZSBkcml2ZXIKPiBpbnRlcm5hbGx5IHdpbGwgY29udmVydCB0aGVz ZSB2YWx1ZSB0byBuYW5kIHBhZ2VzLgo+IAo+IE9uIHVzZXIgcmVhZC93cml0ZSB0aGUgcGFnZSBp cyBjaGVja2VkIGFuZCBpZiBpdCdzIGEgYm9vdCBwYWdlIHRoZQo+IGNvcnJlY3QgbGF5b3V0IGlz IHVzZWQuCj4gCj4gU2lnbmVkLW9mZi1ieTogQW5zdWVsIFNtaXRoIDxhbnN1ZWxzbXRoQGdtYWls LmNvbT4KPiAtLS0KPiAgZHJpdmVycy9tdGQvbmFuZC9yYXcvcWNvbV9uYW5kYy5jIHwgMjA0ICsr KysrKysrKysrKysrKysrKysrKysrKysrKysrLQo+ICAxIGZpbGUgY2hhbmdlZCwgMTk5IGluc2Vy dGlvbnMoKyksIDUgZGVsZXRpb25zKC0pCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvbXRkL25h bmQvcmF3L3Fjb21fbmFuZGMuYyBiL2RyaXZlcnMvbXRkL25hbmQvcmF3L3Fjb21fbmFuZGMuYwo+ IGluZGV4IDdmYmJkM2U3Nzg0Yy4uMjlhMTY1MzRiZWUzIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMv bXRkL25hbmQvcmF3L3Fjb21fbmFuZGMuYwo+ICsrKyBiL2RyaXZlcnMvbXRkL25hbmQvcmF3L3Fj b21fbmFuZGMuYwo+IEBAIC04MCw4ICs4MCwxMCBAQAo+ICAjZGVmaW5lCURJU0FCTEVfU1RBVFVT X0FGVEVSX1dSSVRFCTQKPiAgI2RlZmluZQlDV19QRVJfUEFHRQkJCTYKPiAgI2RlZmluZQlVRF9T SVpFX0JZVEVTCQkJOQo+ICsjZGVmaW5lCVVEX1NJWkVfQllURVNfTUFTSwkJR0VOTUFTSygxOCwg OSkKPiAgI2RlZmluZQlFQ0NfUEFSSVRZX1NJWkVfQllURVNfUlMJMTkKPiAgI2RlZmluZQlTUEFS RV9TSVpFX0JZVEVTCQkyMwo+ICsjZGVmaW5lCVNQQVJFX1NJWkVfQllURVNfTUFTSwkJR0VOTUFT SygyNiwgMjMpCj4gICNkZWZpbmUJTlVNX0FERFJfQ1lDTEVTCQkJMjcKPiAgI2RlZmluZQlTVEFU VVNfQkZSX1JFQUQJCQkzMAo+ICAjZGVmaW5lCVNFVF9SRF9NT0RFX0FGVEVSX1NUQVRVUwkzMQo+ IEBAIC0xMDIsNiArMTA0LDcgQEAKPiAgI2RlZmluZQlFQ0NfTU9ERQkJCTQKPiAgI2RlZmluZQlF Q0NfUEFSSVRZX1NJWkVfQllURVNfQkNICTgKPiAgI2RlZmluZQlFQ0NfTlVNX0RBVEFfQllURVMJ CTE2Cj4gKyNkZWZpbmUJRUNDX05VTV9EQVRBX0JZVEVTX01BU0sJCUdFTk1BU0soMjUsIDE2KQo+ ICAjZGVmaW5lCUVDQ19GT1JDRV9DTEtfT1BFTgkJMzAKPiAgCj4gIC8qIE5BTkRfREVWX0NNRDEg Yml0cyAqLwo+IEBAIC00MTgsNiArNDIxLDE5IEBAIHN0cnVjdCBxY29tX25hbmRfY29udHJvbGxl ciB7Cj4gIAljb25zdCBzdHJ1Y3QgcWNvbV9uYW5kY19wcm9wcyAqcHJvcHM7Cj4gIH07Cj4gIAo+ ICsvKgo+ICsgKiBOQU5EIHNwZWNpYWwgYm9vdCBwYXJ0aXRpb25zCj4gKyAqCj4gKyAqIEBwYWdl X29mZnNldDoJCW9mZnNldCBvZiB0aGUgcGFydGl0aW9uIHdoZXJlIHNwYXJlIGRhdGEgaXMgbm90 IHByb3RlY3RlZAo+ICsgKgkJCQlieSBFQ0MgKHZhbHVlIGluIHBhZ2VzKQo+ICsgKiBAcGFnZV9v ZmZzZXQ6CQlzaXplIG9mIHRoZSBwYXJ0aXRpb24gd2hlcmUgc3BhcmUgZGF0YSBpcyBub3QgcHJv dGVjdGVkCj4gKyAqCQkJCWJ5IEVDQyAodmFsdWUgaW4gcGFnZXMpCj4gKyAqLwo+ICtzdHJ1Y3Qg cWNvbV9uYW5kX2Jvb3RfcGFydGl0aW9uIHsKPiArCXUzMiBwYWdlX29mZnNldDsKPiArCXUzMiBw YWdlX3NpemU7Cj4gK307Cj4gKwo+ICAvKgo+ICAgKiBOQU5EIGNoaXAgc3RydWN0dXJlCj4gICAq Cj4gQEAgLTQzNCw2ICs0NTAsOCBAQCBzdHJ1Y3QgcWNvbV9uYW5kX2NvbnRyb2xsZXIgewo+ICAg KiBAZWNjX2J5dGVzX2h3OgkJRUNDIGJ5dGVzIHVzZWQgYnkgY29udHJvbGxlciBoYXJkd2FyZSBm b3IgdGhpcwo+ICAgKgkJCQljaGlwCj4gICAqCj4gKyAqIEBjb2Rld29yZF9maXh1cDoJCWtlZXAg dHJhY2sgb2YgdGhlIGN1cnJlbnQgbGF5b3V0IHVzZWQgYnkKPiArICoJCQkJdGhlIGRyaXZlciBm b3IgcmVhZC93cml0ZSBvcGVyYXRpb24uCj4gICAqIEB1c2VfZWNjOgkJCXJlcXVlc3QgdGhlIGNv bnRyb2xsZXIgdG8gdXNlIEVDQyBmb3IgdGhlCj4gICAqCQkJCXVwY29taW5nIHJlYWQvd3JpdGUK PiAgICogQGJjaF9lbmFibGVkOgkJZmxhZyB0byB0ZWxsIHdoZXRoZXIgQkNIIEVDQyBtb2RlIGlz IHVzZWQKPiBAQCAtNDQ1LDYgKzQ2MywxMSBAQCBzdHJ1Y3QgcWNvbV9uYW5kX2NvbnRyb2xsZXIg ewo+ICAgKiBAY2ZnMCwgY2ZnMSwgY2ZnMF9yYXcuLjoJTkFORGMgcmVnaXN0ZXIgY29uZmlndXJh dGlvbnMgbmVlZGVkIGZvcgo+ICAgKgkJCQllY2Mvbm9uLWVjYyBtb2RlIGZvciB0aGUgY3VycmVu dCBuYW5kIGZsYXNoCj4gICAqCQkJCWRldmljZQo+ICsgKgo+ICsgKiBAbnJfYm9vdF9wYXJ0aXRp b25zOgkJY291bnQgb2YgdGhlIGJvb3QgcGFydGl0aW9ucyB3aGVyZSBzcGFyZSBkYXRhIGlzIG5v dAo+ICsgKgkJCQlwcm90ZWN0ZWQgYnkgRUNDCj4gKyAqIEBib290X3BhcnRpdGlvbnM6CQlhcnJh eSBvZiBib290IHBhcnRpdGlvbnMgd2hlcmUgb2Zmc2V0IGFuZCBzaXplIG9mIHRoZQo+ICsgKgkJ CQlib290IHBhcnRpdGlvbnMgYXJlIHN0b3JlZAo+ICAgKi8KPiAgc3RydWN0IHFjb21fbmFuZF9o b3N0IHsKPiAgCXN0cnVjdCBuYW5kX2NoaXAgY2hpcDsKPiBAQCAtNDU3LDYgKzQ4MCw3IEBAIHN0 cnVjdCBxY29tX25hbmRfaG9zdCB7Cj4gIAlpbnQgc3BhcmVfYnl0ZXM7Cj4gIAlpbnQgYmJtX3Np emU7Cj4gIAo+ICsJYm9vbCBjb2Rld29yZF9maXh1cDsKPiAgCWJvb2wgdXNlX2VjYzsKPiAgCWJv b2wgYmNoX2VuYWJsZWQ7Cj4gIAl1OCBzdGF0dXM7Cj4gQEAgLTQ2OCw2ICs0OTIsOSBAQCBzdHJ1 Y3QgcWNvbV9uYW5kX2hvc3Qgewo+ICAJdTMyIGVjY19iY2hfY2ZnOwo+ICAJdTMyIGNscmZsYXNo c3RhdHVzOwo+ICAJdTMyIGNscnJlYWRzdGF0dXM7Cj4gKwo+ICsJaW50IG5yX2Jvb3RfcGFydGl0 aW9uczsKPiArCXN0cnVjdCBxY29tX25hbmRfYm9vdF9wYXJ0aXRpb24gKmJvb3RfcGFydGl0aW9u czsKPiAgfTsKPiAgCj4gIC8qCj4gQEAgLTQ3Nyw2ICs1MDQsNyBAQCBzdHJ1Y3QgcWNvbV9uYW5k X2hvc3Qgewo+ICAgKiBAaXNfYmFtIC0gd2hldGhlciBOQU5EIGNvbnRyb2xsZXIgaXMgdXNpbmcg QkFNCj4gICAqIEBpc19xcGljIC0gd2hldGhlciBOQU5EIENUUkwgaXMgcGFydCBvZiBxcGljIElQ Cj4gICAqIEBxcGljX3YyIC0gZmxhZyB0byBpbmRpY2F0ZSBRUElDIElQIHZlcnNpb24gMgo+ICsg KiBAdXNlX2NvZGV3b3JkX2ZpeHVwIC0gd2hldGhlciBOQU5EIGhhcyBkaWZmZXJlbnQgbGF5b3V0 IGZvciBib290IHBhcnRpdGlvbnMKPiAgICogQGRldl9jbWRfcmVnX3N0YXJ0IC0gTkFORF9ERVZf Q01EXyogcmVnaXN0ZXJzIHN0YXJ0aW5nIG9mZnNldAo+ICAgKi8KPiAgc3RydWN0IHFjb21fbmFu ZGNfcHJvcHMgewo+IEBAIC00ODQsNiArNTEyLDcgQEAgc3RydWN0IHFjb21fbmFuZGNfcHJvcHMg ewo+ICAJYm9vbCBpc19iYW07Cj4gIAlib29sIGlzX3FwaWM7Cj4gIAlib29sIHFwaWNfdjI7Cj4g Kwlib29sIHVzZV9jb2Rld29yZF9maXh1cDsKPiAgCXUzMiBkZXZfY21kX3JlZ19zdGFydDsKPiAg fTsKPiAgCj4gQEAgLTE3MDMsNyArMTczMiw3IEBAIHFjb21fbmFuZGNfcmVhZF9jd19yYXcoc3Ry dWN0IG10ZF9pbmZvICptdGQsIHN0cnVjdCBuYW5kX2NoaXAgKmNoaXAsCj4gIAlkYXRhX3NpemUx ID0gbXRkLT53cml0ZXNpemUgLSBob3N0LT5jd19zaXplICogKGVjYy0+c3RlcHMgLSAxKTsKPiAg CW9vYl9zaXplMSA9IGhvc3QtPmJibV9zaXplOwo+ICAKPiAtCWlmIChxY29tX25hbmRjX2lzX2xh c3RfY3coZWNjLCBjdykpIHsKPiArCWlmIChxY29tX25hbmRjX2lzX2xhc3RfY3coZWNjLCBjdykg JiYgIWhvc3QtPmNvZGV3b3JkX2ZpeHVwKSB7Cj4gIAkJZGF0YV9zaXplMiA9IGVjYy0+c2l6ZSAt IGRhdGFfc2l6ZTEgLQo+ICAJCQkgICAgICgoZWNjLT5zdGVwcyAtIDEpICogNCk7Cj4gIAkJb29i X3NpemUyID0gKGVjYy0+c3RlcHMgKiA0KSArIGhvc3QtPmVjY19ieXRlc19odyArCj4gQEAgLTE3 ODQsNyArMTgxMyw3IEBAIGNoZWNrX2Zvcl9lcmFzZWRfcGFnZShzdHJ1Y3QgcWNvbV9uYW5kX2hv c3QgKmhvc3QsIHU4ICpkYXRhX2J1ZiwKPiAgCX0KPiAgCj4gIAlmb3JfZWFjaF9zZXRfYml0KGN3 LCAmdW5jb3JyZWN0YWJsZV9jd3MsIGVjYy0+c3RlcHMpIHsKPiAtCQlpZiAocWNvbV9uYW5kY19p c19sYXN0X2N3KGVjYywgY3cpKSB7Cj4gKwkJaWYgKHFjb21fbmFuZGNfaXNfbGFzdF9jdyhlY2Ms IGN3KSAmJiAhaG9zdC0+Y29kZXdvcmRfZml4dXApIHsKPiAgCQkJZGF0YV9zaXplID0gZWNjLT5z aXplIC0gKChlY2MtPnN0ZXBzIC0gMSkgKiA0KTsKPiAgCQkJb29iX3NpemUgPSAoZWNjLT5zdGVw cyAqIDQpICsgaG9zdC0+ZWNjX2J5dGVzX2h3Owo+ICAJCX0gZWxzZSB7Cj4gQEAgLTE5NDIsNyAr MTk3MSw3IEBAIHN0YXRpYyBpbnQgcmVhZF9wYWdlX2VjYyhzdHJ1Y3QgcWNvbV9uYW5kX2hvc3Qg Kmhvc3QsIHU4ICpkYXRhX2J1ZiwKPiAgCWZvciAoaSA9IDA7IGkgPCBlY2MtPnN0ZXBzOyBpKysp IHsKPiAgCQlpbnQgZGF0YV9zaXplLCBvb2Jfc2l6ZTsKPiAgCj4gLQkJaWYgKHFjb21fbmFuZGNf aXNfbGFzdF9jdyhlY2MsIGkpKSB7Cj4gKwkJaWYgKHFjb21fbmFuZGNfaXNfbGFzdF9jdyhlY2Ms IGkpICYmICFob3N0LT5jb2Rld29yZF9maXh1cCkgewo+ICAJCQlkYXRhX3NpemUgPSBlY2MtPnNp emUgLSAoKGVjYy0+c3RlcHMgLSAxKSA8PCAyKTsKPiAgCQkJb29iX3NpemUgPSAoZWNjLT5zdGVw cyA8PCAyKSArIGhvc3QtPmVjY19ieXRlc19odyArCj4gIAkJCQkgICBob3N0LT5zcGFyZV9ieXRl czsKPiBAQCAtMjAzOSw2ICsyMDY4LDc4IEBAIHN0YXRpYyBpbnQgY29weV9sYXN0X2N3KHN0cnVj dCBxY29tX25hbmRfaG9zdCAqaG9zdCwgaW50IHBhZ2UpCj4gIAlyZXR1cm4gcmV0Owo+ICB9Cj4g IAo+ICtzdGF0aWMgYm9vbCBxY29tX25hbmRjX2lzX2Jvb3RfcGFydGl0aW9uKHN0cnVjdCBxY29t X25hbmRfaG9zdCAqaG9zdCwgaW50IHBhZ2UpCj4gK3sKPiArCXN0cnVjdCBxY29tX25hbmRfYm9v dF9wYXJ0aXRpb24gKmJvb3RfcGFydGl0aW9uOwo+ICsJdTMyIHN0YXJ0LCBlbmQ7Cj4gKwlpbnQg aTsKPiArCj4gKwkvKgo+ICsJICogU2luY2UgdGhlIGZyZXF1ZW50IGFjY2VzcyB3aWxsIGJlIHRv IHRoZSBub24tYm9vdCBwYXJ0aXRpb25zIGxpa2Ugcm9vdGZzLAo+ICsJICogb3B0aW1pemUgdGhl IHBhZ2UgY2hlY2sgYnk6Cj4gKwo+ICsJICogMS4gQ2hlY2tpbmcgaWYgdGhlIHBhZ2UgbGllcyBh ZnRlciB0aGUgbGFzdCBib290IHBhcnRpdGlvbi4KClRoaXMgaXMgbm90IGltcGxlbWVudGVkIGlu IGNvZGUuCgo+ICsJICogMi4gQ2hlY2tpbmcgZnJvbSB0aGUgYm9vdCBwYXJ0aXRpb24gZW5kLgo+ ICsJICoKCkkgdGhpbmsgd2UgY2FuIGxlYXZlIHRoZSBiZWxvdyBleGFtcGxlIHBhcnQuIEkganVz dCBhc2tlZCB0byBpbmNsdWRlIHRoZSBhY3R1YWwKdXNlY2FzZSBhbmQgYWJvdmUgcG9pbnRzIHN1 ZmZpY2UuCgo+ICsJICogVGhpcyBjb21lcyBmcm9tIHRoZSBmYWN0IHRoYXQgYW4gZXhhbXBsZSBw YXJ0aXRpb24gdGFibGUgaXM6Cj4gKwkgKiBtdGQwOiAwMGM4MDAwMCAwMDAyMDAwMCAicWNhZGF0 YSIJKHJlcXVpcmUgY29kZXdvcmQgZml4KQo+ICsJICogbXRkMTogMDA1MDAwMDAgMDAwMjAwMDAg IkFQUFNCTCIJKHJlcXVpcmUgY29kZXdvcmQgZml4KQo+ICsJICogbXRkMjogMDAwODAwMDAgMDAw MjAwMDAgIkFQUFNCTEVOViIJKGRvZXNuJ3QgcmVxdWlyZSBjb2Rld29yZCBmaXgpCj4gKwkgKiBt dGQzOiAwMDE0MDAwMCAwMDAyMDAwMCAiYXJ0IgkoZG9lc24ndCByZXF1aXJlIGNvZGV3b3JkIGZp eCkKPiArCSAqIG10ZDQ6IDAwMTQwMDAwIDAwMDIwMDAwICJhcnRiYWsiCShkb2Vzbid0IHJlcXVp cmUgY29kZXdvcmQgZml4KQo+ICsJICogbXRkNTogMDA0MDAwMDAgMDAwMjAwMDAgImtlcm5lbCIJ KGRvZXNuJ3QgcmVxdWlyZSBjb2Rld29yZCBmaXgpCj4gKwkgKiBtdGQ2OiAwNjA4MDAwMCAwMDAy MDAwMCAidWJpIgkoZG9lc24ndCByZXF1aXJlIGNvZGV3b3JkIGZpeCkKPiArCSAqIG10ZDc6IDAw NzAwMDAwIDAwMDIwMDAwICJyZXNlcnZlIgkoZG9lc24ndCByZXF1aXJlIGNvZGV3b3JkIGZpeCkK PiArCSAqCj4gKwkgKiB3aGVyZSB0aGUgYm9vdCBwYXJ0aXRpb24gYXJlIGFsd2F5cyB0aGUgZmly c3QgcGFydGl0aW9uIGFuZCByb290ZnMKPiArCSAqIHBhcnRpdGlvbiBhcmUgYXQgdGhlIGVuZC4K PiArCSAqCj4gKwkgKiBEZWZpbmluZyBhIGJpZyBzaW5nbGUgYm9vdCBwYXJ0aXRpb24gaXMgbm90 IHBvc3NpYmxlIHNpbmNlIHNvbWUKPiArCSAqIGRldmljZSBoYXZlIHRoZSBmb2xsb3dpbmcgcGFy dGl0aW9uIHRhYmxlOgo+ICsJICogbXRkMDogMDBjODAwMDAgMDAwMjAwMDAgInFjYWRhdGEiIChy ZXF1aXJlIGNvZGV3b3JkIGZpeCkKPiArCSAqIG10ZDE6IDAwNTAwMDAwIDAwMDIwMDAwICJBUFBT QkwiICAocmVxdWlyZSBjb2Rld29yZCBmaXgpCj4gKwkgKiBtdGQyOiAwMDA4MDAwMCAwMDAyMDAw MCAiQVBQU0JMRU5WIiAoZG9lc24ndCByZXF1aXJlIGNvZGV3b3JkIGZpeCkKPiArCSAqIG10ZDM6 IDAwMTQwMDAwIDAwMDIwMDAwICJBUFBTQkwyIiAgKHJlcXVpcmUgY29kZXdvcmQgZml4KQo+ICsJ ICoKPiArCSAqIHdoZXJlIGEgYmFja3VwIHBhcnRpdGlvbiBpcyBwbGFjZWQgYWZ0ZXIgYSBwYXJ0 aXRpb24gd2hlcmUgdGhlCj4gKwkgKiBjb2Rld29yZCBmaXggc2hvdWxkIG5vdCBiZSB1c2VkLgo+ ICsJICovCj4gKwlmb3IgKGkgPSBob3N0LT5ucl9ib290X3BhcnRpdGlvbnMgLSAxOyBpID49IDA7 IGktLSkgewo+ICsJCWJvb3RfcGFydGl0aW9uID0gJmhvc3QtPmJvb3RfcGFydGl0aW9uc1tpXTsK PiArCQlzdGFydCA9IGJvb3RfcGFydGl0aW9uLT5wYWdlX29mZnNldDsKPiArCQllbmQgPSBzdGFy dCArIGJvb3RfcGFydGl0aW9uLT5wYWdlX3NpemU7Cj4gKwo+ICsJCWlmIChwYWdlIDwgZW5kICYm IHBhZ2UgPj0gc3RhcnQpCj4gKwkJCXJldHVybiB0cnVlOwo+ICsJfQo+ICsKPiArCXJldHVybiBm YWxzZTsKPiArfQo+ICsKPiArc3RhdGljIHZvaWQKPiArcWNvbV9uYW5kY19jb2Rld29yZF9maXh1 cChzdHJ1Y3QgcWNvbV9uYW5kX2hvc3QgKmhvc3QsIGludCBwYWdlKQo+ICt7Cj4gKwlib29sIGNv ZGV3b3JkX2ZpeHVwID0gcWNvbV9uYW5kY19pc19ib290X3BhcnRpdGlvbihob3N0LCBwYWdlKTsK PiArCj4gKwkvKiBTa2lwIGNvbmYgd3JpdGUgaWYgd2UgYXJlIGFscmVhZHkgaW4gdGhlIGNvcnJl Y3QgbW9kZSAqLwo+ICsJaWYgKGNvZGV3b3JkX2ZpeHVwID09IGhvc3QtPmNvZGV3b3JkX2ZpeHVw KQo+ICsJCXJldHVybjsKPiArCj4gKwlob3N0LT5jb2Rld29yZF9maXh1cCA9IGNvZGV3b3JkX2Zp eHVwOwo+ICsKPiArCWhvc3QtPmN3X2RhdGEgPSBjb2Rld29yZF9maXh1cCA/IDUxMiA6IDUxNjsK PiArCWhvc3QtPnNwYXJlX2J5dGVzID0gaG9zdC0+Y3dfc2l6ZSAtIGhvc3QtPmVjY19ieXRlc19o dyAtCj4gKwkJCSAgICBob3N0LT5iYm1fc2l6ZSAtIGhvc3QtPmN3X2RhdGE7Cj4gKwo+ICsJaG9z dC0+Y2ZnMCAmPSB+KFNQQVJFX1NJWkVfQllURVNfTUFTSyB8IFVEX1NJWkVfQllURVNfTUFTSyk7 Cj4gKwlob3N0LT5jZmcwIHw9IGhvc3QtPnNwYXJlX2J5dGVzIDw8IFNQQVJFX1NJWkVfQllURVMg fAo+ICsJCSAgICAgIGhvc3QtPmN3X2RhdGEgPDwgVURfU0laRV9CWVRFUzsKPiArCj4gKwlob3N0 LT5lY2NfYmNoX2NmZyAmPSB+RUNDX05VTV9EQVRBX0JZVEVTX01BU0s7Cj4gKwlob3N0LT5lY2Nf YmNoX2NmZyB8PSBob3N0LT5jd19kYXRhIDw8IEVDQ19OVU1fREFUQV9CWVRFUzsKPiArCWhvc3Qt PmVjY19idWZfY2ZnID0gKGhvc3QtPmN3X2RhdGEgLSAxKSA8PCBOVU1fU1RFUFM7Cj4gK30KPiAr Cj4gIC8qIGltcGxlbWVudHMgZWNjLT5yZWFkX3BhZ2UoKSAqLwo+ICBzdGF0aWMgaW50IHFjb21f bmFuZGNfcmVhZF9wYWdlKHN0cnVjdCBuYW5kX2NoaXAgKmNoaXAsIHVpbnQ4X3QgKmJ1ZiwKPiAg CQkJCWludCBvb2JfcmVxdWlyZWQsIGludCBwYWdlKQo+IEBAIC0yMDQ3LDYgKzIxNDgsOSBAQCBz dGF0aWMgaW50IHFjb21fbmFuZGNfcmVhZF9wYWdlKHN0cnVjdCBuYW5kX2NoaXAgKmNoaXAsIHVp bnQ4X3QgKmJ1ZiwKPiAgCXN0cnVjdCBxY29tX25hbmRfY29udHJvbGxlciAqbmFuZGMgPSBnZXRf cWNvbV9uYW5kX2NvbnRyb2xsZXIoY2hpcCk7Cj4gIAl1OCAqZGF0YV9idWYsICpvb2JfYnVmID0g TlVMTDsKPiAgCj4gKwlpZiAoaG9zdC0+bnJfYm9vdF9wYXJ0aXRpb25zKQo+ICsJCXFjb21fbmFu ZGNfY29kZXdvcmRfZml4dXAoaG9zdCwgcGFnZSk7Cj4gKwo+ICAJbmFuZF9yZWFkX3BhZ2Vfb3Ao Y2hpcCwgcGFnZSwgMCwgTlVMTCwgMCk7Cj4gIAlkYXRhX2J1ZiA9IGJ1ZjsKPiAgCW9vYl9idWYg PSBvb2JfcmVxdWlyZWQgPyBjaGlwLT5vb2JfcG9pIDogTlVMTDsKPiBAQCAtMjA2Niw2ICsyMTcw LDkgQEAgc3RhdGljIGludCBxY29tX25hbmRjX3JlYWRfcGFnZV9yYXcoc3RydWN0IG5hbmRfY2hp cCAqY2hpcCwgdWludDhfdCAqYnVmLAo+ICAJaW50IGN3LCByZXQ7Cj4gIAl1OCAqZGF0YV9idWYg PSBidWYsICpvb2JfYnVmID0gY2hpcC0+b29iX3BvaTsKPiAgCj4gKwlpZiAoaG9zdC0+bnJfYm9v dF9wYXJ0aXRpb25zKQo+ICsJCXFjb21fbmFuZGNfY29kZXdvcmRfZml4dXAoaG9zdCwgcGFnZSk7 Cj4gKwo+ICAJZm9yIChjdyA9IDA7IGN3IDwgZWNjLT5zdGVwczsgY3crKykgewo+ICAJCXJldCA9 IHFjb21fbmFuZGNfcmVhZF9jd19yYXcobXRkLCBjaGlwLCBkYXRhX2J1Ziwgb29iX2J1ZiwKPiAg CQkJCQkgICAgIHBhZ2UsIGN3KTsKPiBAQCAtMjA4Niw2ICsyMTkzLDkgQEAgc3RhdGljIGludCBx Y29tX25hbmRjX3JlYWRfb29iKHN0cnVjdCBuYW5kX2NoaXAgKmNoaXAsIGludCBwYWdlKQo+ICAJ c3RydWN0IHFjb21fbmFuZF9jb250cm9sbGVyICpuYW5kYyA9IGdldF9xY29tX25hbmRfY29udHJv bGxlcihjaGlwKTsKPiAgCXN0cnVjdCBuYW5kX2VjY19jdHJsICplY2MgPSAmY2hpcC0+ZWNjOwo+ ICAKPiArCWlmIChob3N0LT5ucl9ib290X3BhcnRpdGlvbnMpCj4gKwkJcWNvbV9uYW5kY19jb2Rl d29yZF9maXh1cChob3N0LCBwYWdlKTsKPiArCj4gIAljbGVhcl9yZWFkX3JlZ3MobmFuZGMpOwo+ ICAJY2xlYXJfYmFtX3RyYW5zYWN0aW9uKG5hbmRjKTsKPiAgCj4gQEAgLTIxMDYsNiArMjIxNiw5 IEBAIHN0YXRpYyBpbnQgcWNvbV9uYW5kY193cml0ZV9wYWdlKHN0cnVjdCBuYW5kX2NoaXAgKmNo aXAsIGNvbnN0IHVpbnQ4X3QgKmJ1ZiwKPiAgCXU4ICpkYXRhX2J1ZiwgKm9vYl9idWY7Cj4gIAlp bnQgaSwgcmV0Owo+ICAKPiArCWlmIChob3N0LT5ucl9ib290X3BhcnRpdGlvbnMpCj4gKwkJcWNv bV9uYW5kY19jb2Rld29yZF9maXh1cChob3N0LCBwYWdlKTsKPiArCj4gIAluYW5kX3Byb2dfcGFn ZV9iZWdpbl9vcChjaGlwLCBwYWdlLCAwLCBOVUxMLCAwKTsKPiAgCj4gIAljbGVhcl9yZWFkX3Jl Z3MobmFuZGMpOwo+IEBAIC0yMTIxLDcgKzIyMzQsNyBAQCBzdGF0aWMgaW50IHFjb21fbmFuZGNf d3JpdGVfcGFnZShzdHJ1Y3QgbmFuZF9jaGlwICpjaGlwLCBjb25zdCB1aW50OF90ICpidWYsCj4g IAlmb3IgKGkgPSAwOyBpIDwgZWNjLT5zdGVwczsgaSsrKSB7Cj4gIAkJaW50IGRhdGFfc2l6ZSwg b29iX3NpemU7Cj4gIAo+IC0JCWlmIChxY29tX25hbmRjX2lzX2xhc3RfY3coZWNjLCBpKSkgewo+ ICsJCWlmIChxY29tX25hbmRjX2lzX2xhc3RfY3coZWNjLCBpKSAmJiAhaG9zdC0+Y29kZXdvcmRf Zml4dXApIHsKPiAgCQkJZGF0YV9zaXplID0gZWNjLT5zaXplIC0gKChlY2MtPnN0ZXBzIC0gMSkg PDwgMik7Cj4gIAkJCW9vYl9zaXplID0gKGVjYy0+c3RlcHMgPDwgMikgKyBob3N0LT5lY2NfYnl0 ZXNfaHcgKwo+ICAJCQkJICAgaG9zdC0+c3BhcmVfYnl0ZXM7Cj4gQEAgLTIxNzgsNiArMjI5MSw5 IEBAIHN0YXRpYyBpbnQgcWNvbV9uYW5kY193cml0ZV9wYWdlX3JhdyhzdHJ1Y3QgbmFuZF9jaGlw ICpjaGlwLAo+ICAJdTggKmRhdGFfYnVmLCAqb29iX2J1ZjsKPiAgCWludCBpLCByZXQ7Cj4gIAo+ ICsJaWYgKGhvc3QtPm5yX2Jvb3RfcGFydGl0aW9ucykKPiArCQlxY29tX25hbmRjX2NvZGV3b3Jk X2ZpeHVwKGhvc3QsIHBhZ2UpOwo+ICsKPiAgCW5hbmRfcHJvZ19wYWdlX2JlZ2luX29wKGNoaXAs IHBhZ2UsIDAsIE5VTEwsIDApOwo+ICAJY2xlYXJfcmVhZF9yZWdzKG5hbmRjKTsKPiAgCWNsZWFy X2JhbV90cmFuc2FjdGlvbihuYW5kYyk7Cj4gQEAgLTIxOTYsNyArMjMxMiw3IEBAIHN0YXRpYyBp bnQgcWNvbV9uYW5kY193cml0ZV9wYWdlX3JhdyhzdHJ1Y3QgbmFuZF9jaGlwICpjaGlwLAo+ICAJ CWRhdGFfc2l6ZTEgPSBtdGQtPndyaXRlc2l6ZSAtIGhvc3QtPmN3X3NpemUgKiAoZWNjLT5zdGVw cyAtIDEpOwo+ICAJCW9vYl9zaXplMSA9IGhvc3QtPmJibV9zaXplOwo+ICAKPiAtCQlpZiAocWNv bV9uYW5kY19pc19sYXN0X2N3KGVjYywgaSkpIHsKPiArCQlpZiAocWNvbV9uYW5kY19pc19sYXN0 X2N3KGVjYywgaSkgJiYgIWhvc3QtPmNvZGV3b3JkX2ZpeHVwKSB7Cj4gIAkJCWRhdGFfc2l6ZTIg PSBlY2MtPnNpemUgLSBkYXRhX3NpemUxIC0KPiAgCQkJCSAgICAgKChlY2MtPnN0ZXBzIC0gMSkg PDwgMik7Cj4gIAkJCW9vYl9zaXplMiA9IChlY2MtPnN0ZXBzIDw8IDIpICsgaG9zdC0+ZWNjX2J5 dGVzX2h3ICsKPiBAQCAtMjI1Niw2ICsyMzcyLDkgQEAgc3RhdGljIGludCBxY29tX25hbmRjX3dy aXRlX29vYihzdHJ1Y3QgbmFuZF9jaGlwICpjaGlwLCBpbnQgcGFnZSkKPiAgCWludCBkYXRhX3Np emUsIG9vYl9zaXplOwo+ICAJaW50IHJldDsKPiAgCj4gKwlpZiAoaG9zdC0+bnJfYm9vdF9wYXJ0 aXRpb25zKQo+ICsJCXFjb21fbmFuZGNfY29kZXdvcmRfZml4dXAoaG9zdCwgcGFnZSk7Cj4gKwo+ ICAJaG9zdC0+dXNlX2VjYyA9IHRydWU7Cj4gIAljbGVhcl9iYW1fdHJhbnNhY3Rpb24obmFuZGMp Owo+ICAKPiBAQCAtMjkwNCw2ICszMDIzLDc0IEBAIHN0YXRpYyBpbnQgcWNvbV9uYW5kY19zZXR1 cChzdHJ1Y3QgcWNvbV9uYW5kX2NvbnRyb2xsZXIgKm5hbmRjKQo+ICAKPiAgc3RhdGljIGNvbnN0 IGNoYXIgKiBjb25zdCBwcm9iZXNbXSA9IHsgImNtZGxpbmVwYXJ0IiwgIm9mcGFydCIsICJxY29t c21lbSIsIE5VTEwgfTsKPiAgCj4gK3N0YXRpYyBpbnQgcWNvbV9uYW5kX2hvc3RfcGFyc2VfYm9v dF9wYXJ0aXRpb25zKHN0cnVjdCBxY29tX25hbmRfY29udHJvbGxlciAqbmFuZGMsCj4gKwkJCQkJ CXN0cnVjdCBxY29tX25hbmRfaG9zdCAqaG9zdCwKPiArCQkJCQkJc3RydWN0IGRldmljZV9ub2Rl ICpkbikKPiArewo+ICsJc3RydWN0IG5hbmRfY2hpcCAqY2hpcCA9ICZob3N0LT5jaGlwOwo+ICsJ c3RydWN0IG10ZF9pbmZvICptdGQgPSBuYW5kX3RvX210ZChjaGlwKTsKPiArCXN0cnVjdCBxY29t X25hbmRfYm9vdF9wYXJ0aXRpb24gKmJvb3RfcGFydGl0aW9uOwo+ICsJc3RydWN0IGRldmljZSAq ZGV2ID0gbmFuZGMtPmRldjsKPiArCWludCBwYXJ0aXRpb25zX2NvdW50LCBpLCBqLCByZXQ7Cj4g Kwo+ICsJaWYgKCFvZl9maW5kX3Byb3BlcnR5KGRuLCAicWNvbSxib290LXBhcnRpdGlvbnMiLCBO VUxMKSkKPiArCQlyZXR1cm4gMDsKPiArCj4gKwlwYXJ0aXRpb25zX2NvdW50ID0gb2ZfcHJvcGVy dHlfY291bnRfdTMyX2VsZW1zKGRuLCAicWNvbSxib290LXBhcnRpdGlvbnMiKTsKPiArCWlmIChw YXJ0aXRpb25zX2NvdW50IDw9IDApIHsKPiArCQlkZXZfZXJyKGRldiwgIkVycm9yIHBhcnNpbmcg Ym9vdCBwYXJ0aXRpb25cbiIpOwo+ICsJCXJldHVybiByZXQ7Cj4gKwl9Cj4gKwo+ICsJaG9zdC0+ bnJfYm9vdF9wYXJ0aXRpb25zID0gcGFydGl0aW9uc19jb3VudCAvIDI7Cj4gKwlob3N0LT5ib290 X3BhcnRpdGlvbnMgPSBkZXZtX2tjYWxsb2MoZGV2LCBob3N0LT5ucl9ib290X3BhcnRpdGlvbnMs Cj4gKwkJCQkJICAgICBzaXplb2YoKmhvc3QtPmJvb3RfcGFydGl0aW9ucyksIEdGUF9LRVJORUwp Owo+ICsJaWYgKCFob3N0LT5ib290X3BhcnRpdGlvbnMpIHsKPiArCQlob3N0LT5ucl9ib290X3Bh cnRpdGlvbnMgPSAwOwo+ICsJCXJldHVybiAtRU5PTUVNOwo+ICsJfQo+ICsKPiArCWZvciAoaSA9 IDAsIGogPSAwOyBpIDwgaG9zdC0+bnJfYm9vdF9wYXJ0aXRpb25zOyBpKyssIGogKz0gMikgewo+ ICsJCWJvb3RfcGFydGl0aW9uID0gJmhvc3QtPmJvb3RfcGFydGl0aW9uc1tpXTsKPiArCj4gKwkJ cmV0ID0gb2ZfcHJvcGVydHlfcmVhZF91MzJfaW5kZXgoZG4sICJxY29tLGJvb3QtcGFydGl0aW9u cyIsIGosCj4gKwkJCQkJCSAmYm9vdF9wYXJ0aXRpb24tPnBhZ2Vfb2Zmc2V0KTsKPiArCQlpZiAo cmV0KSB7Cj4gKwkJCWRldl9lcnIoZGV2LCAiRXJyb3IgcGFyc2luZyBib290IHBhcnRpdGlvbiBv ZmZzZXQgYXQgaW5kZXggJWQiLCBpKTsKCkVyci4uLiBZb3UgbWlzc2VkIGFkZGluZyBuZXdsaW5l IGhlcmUgYW5kIGJlbG93LgoKPiArCQkJaG9zdC0+bnJfYm9vdF9wYXJ0aXRpb25zID0gMDsKPiAr CQkJcmV0dXJuIHJldDsKPiArCQl9Cj4gKwo+ICsJCWlmIChib290X3BhcnRpdGlvbi0+cGFnZV9v ZmZzZXQgJSBtdGQtPndyaXRlc2l6ZSkgewo+ICsJCQlkZXZfZXJyKGRldiwgIkJvb3QgcGFydGl0 aW9uIG9mZnNldCBub3QgbXVsdGlwbGUgb2Ygd3JpdGVzaXplIGF0IGluZGV4ICVpXG4iLAo+ICsJ CQkJaSk7Cj4gKwkJCWhvc3QtPm5yX2Jvb3RfcGFydGl0aW9ucyA9IDA7Cj4gKwkJCXJldHVybiAt RUlOVkFMOwo+ICsJCX0KPiArCQkvKiBDb252ZXJ0IG9mZnNldCB0byBuYW5kIHBhZ2VzICovCj4g KwkJYm9vdF9wYXJ0aXRpb24tPnBhZ2Vfb2Zmc2V0IC89IG10ZC0+d3JpdGVzaXplOwo+ICsKPiAr CQlyZXQgPSBvZl9wcm9wZXJ0eV9yZWFkX3UzMl9pbmRleChkbiwgInFjb20sYm9vdC1wYXJ0aXRp b25zIiwgaiArIDEsCj4gKwkJCQkJCSAmYm9vdF9wYXJ0aXRpb24tPnBhZ2Vfc2l6ZSk7Cj4gKwkJ aWYgKHJldCkgewo+ICsJCQlkZXZfZXJyKGRldiwgIkVycm9yIHBhcnNpbmcgYm9vdCBwYXJ0aXRp b24gc2l6ZSBhdCBpbmRleCAlZFxuIiwgaSk7Cj4gKwkJCWhvc3QtPm5yX2Jvb3RfcGFydGl0aW9u cyA9IDA7Cj4gKwkJCXJldHVybiByZXQ7Cj4gKwkJfQo+ICsKPiArCQlpZiAoYm9vdF9wYXJ0aXRp b24tPnBhZ2Vfc2l6ZSAlIG10ZC0+d3JpdGVzaXplKSB7Cj4gKwkJCWRldl9lcnIoZGV2LCAiQm9v dCBwYXJ0aXRpb24gc2l6ZSBub3QgbXVsdGlwbGUgb2Ygd3JpdGVzaXplIGF0IGluZGV4ICVpIiwK PiArCQkJCWkpOwo+ICsJCQlob3N0LT5ucl9ib290X3BhcnRpdGlvbnMgPSAwOwo+ICsJCQlyZXR1 cm4gLUVJTlZBTDsKPiArCQl9Cj4gKwkJLyogQ29udmVydCBzaXplIHRvIG5hbmQgcGFnZXMgKi8K PiArCQlib290X3BhcnRpdGlvbi0+cGFnZV9zaXplIC89IG10ZC0+d3JpdGVzaXplOwo+ICsJfQo+ ICsKPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ICBzdGF0aWMgaW50IHFjb21fbmFuZF9ob3N0X2lu aXRfYW5kX3JlZ2lzdGVyKHN0cnVjdCBxY29tX25hbmRfY29udHJvbGxlciAqbmFuZGMsCj4gIAkJ CQkJICAgIHN0cnVjdCBxY29tX25hbmRfaG9zdCAqaG9zdCwKPiAgCQkJCQkgICAgc3RydWN0IGRl dmljZV9ub2RlICpkbikKPiBAQCAtMjk3Miw2ICszMTU5LDEyIEBAIHN0YXRpYyBpbnQgcWNvbV9u YW5kX2hvc3RfaW5pdF9hbmRfcmVnaXN0ZXIoc3RydWN0IHFjb21fbmFuZF9jb250cm9sbGVyICpu YW5kYywKPiAgCWlmIChyZXQpCj4gIAkJbmFuZF9jbGVhbnVwKGNoaXApOwo+ICAKPiArCWlmIChu YW5kYy0+cHJvcHMtPnVzZV9jb2Rld29yZF9maXh1cCkgewo+ICsJCXJldCA9IHFjb21fbmFuZF9o b3N0X3BhcnNlX2Jvb3RfcGFydGl0aW9ucyhuYW5kYywgaG9zdCwgZG4pOwo+ICsJCWlmIChyZXQp Cj4gKwkJCXJldHVybiByZXQ7CgpNaXNzZWQgbmFuZF9jbGVhbnVwKCkuCgpUaGFua3MsCk1hbmkK Cj4gKwl9Cj4gKwo+ICAJcmV0dXJuIHJldDsKPiAgfQo+ICAKPiBAQCAtMzEzNyw2ICszMzMwLDcg QEAgc3RhdGljIGludCBxY29tX25hbmRjX3JlbW92ZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpw ZGV2KQo+ICBzdGF0aWMgY29uc3Qgc3RydWN0IHFjb21fbmFuZGNfcHJvcHMgaXBxODA2eF9uYW5k Y19wcm9wcyA9IHsKPiAgCS5lY2NfbW9kZXMgPSAoRUNDX1JTXzRCSVQgfCBFQ0NfQkNIXzhCSVQp LAo+ICAJLmlzX2JhbSA9IGZhbHNlLAo+ICsJLnVzZV9jb2Rld29yZF9maXh1cCA9IHRydWUsCj4g IAkuZGV2X2NtZF9yZWdfc3RhcnQgPSAweDAsCj4gIH07Cj4gIAo+IC0tIAo+IDIuMzYuMQo+IAoK LS0gCuCuruCuo+Cuv+CuteCuo+CvjeCuo+CuqeCvjSDgrprgrqTgrr7grprgrr/grrXgrq7gr40K Cl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpM aW51eCBNVEQgZGlzY3Vzc2lvbiBtYWlsaW5nIGxpc3QKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5v cmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1tdGQvCg==