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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 19/28] target/arm: Introduce helper_exception_with_syndrome
Date: Fri, 10 Jun 2022 17:07:29 +0100	[thread overview]
Message-ID: <20220610160738.2230762-20-peter.maydell@linaro.org> (raw)
In-Reply-To: <20220610160738.2230762-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

With the helper we can use exception_target_el at runtime,
instead of default_exception_el at translate time.
While we're at it, remove the DisasContext parameter from
gen_exception, as it is no longer used.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h    |  1 +
 target/arm/op_helper.c | 10 ++++++++++
 target/arm/translate.c | 18 +++++++++++++-----
 3 files changed, 24 insertions(+), 5 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index db7447d233e..07d45faf495 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -45,6 +45,7 @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32)
 DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
                    i32, i32, i32, i32)
 DEF_HELPER_2(exception_internal, noreturn, env, i32)
+DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32)
 DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32)
 DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32)
 DEF_HELPER_2(exception_swstep, noreturn, env, i32)
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 8a6a3b85516..c5bde1cfcc7 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -399,6 +399,16 @@ void HELPER(exception_with_syndrome_el)(CPUARMState *env, uint32_t excp,
     raise_exception(env, excp, syndrome, target_el);
 }
 
+/*
+ * Raise an exception with the specified syndrome register value
+ * to the default target el.
+ */
+void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
+                                     uint32_t syndrome)
+{
+    raise_exception(env, excp, syndrome, exception_target_el(env));
+}
+
 uint32_t HELPER(cpsr_read)(CPUARMState *env)
 {
     return cpsr_read(env) & ~CPSR_EXEC;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index fcb6ee648b5..81c27e7c70c 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1097,9 +1097,10 @@ static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el)
     gen_exception_el_v(excp, syndrome, tcg_constant_i32(target_el));
 }
 
-static void gen_exception(DisasContext *s, int excp, uint32_t syndrome)
+static void gen_exception(int excp, uint32_t syndrome)
 {
-    gen_exception_el(excp, syndrome, default_exception_el(s));
+    gen_helper_exception_with_syndrome(cpu_env, tcg_constant_i32(excp),
+                                       tcg_constant_i32(syndrome));
 }
 
 static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
@@ -1123,7 +1124,14 @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
 
 void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn)
 {
-    gen_exception_insn_el(s, pc, excp, syn, default_exception_el(s));
+    if (s->aarch64) {
+        gen_a64_set_pc_im(pc);
+    } else {
+        gen_set_condexec(s);
+        gen_set_pc_im(s, pc);
+    }
+    gen_exception(excp, syn);
+    s->base.is_jmp = DISAS_NORETURN;
 }
 
 static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
@@ -9766,7 +9774,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
         switch (dc->base.is_jmp) {
         case DISAS_SWI:
             gen_ss_advance(dc);
-            gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
+            gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
             break;
         case DISAS_HVC:
             gen_ss_advance(dc);
@@ -9835,7 +9843,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
             gen_helper_yield(cpu_env);
             break;
         case DISAS_SWI:
-            gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
+            gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
             break;
         case DISAS_HVC:
             gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
-- 
2.25.1



  parent reply	other threads:[~2022-06-10 16:24 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-10 16:07 [PULL 00/28] target-arm queue Peter Maydell
2022-06-10 16:07 ` [PULL 01/28] target/arm: Mark exception helpers as noreturn Peter Maydell
2022-06-10 16:07 ` [PULL 02/28] target/arm: Add coproc parameter to syn_fp_access_trap Peter Maydell
2022-08-12 14:47   ` Peter Maydell
2022-06-10 16:07 ` [PULL 03/28] target/arm: Move exception_target_el out of line Peter Maydell
2022-06-10 16:07 ` [PULL 04/28] target/arm: Move arm_singlestep_active " Peter Maydell
2022-06-10 16:07 ` [PULL 05/28] target/arm: Move arm_generate_debug_exceptions " Peter Maydell
2022-06-10 16:07 ` [PULL 06/28] target/arm: Use is_a64 in arm_generate_debug_exceptions Peter Maydell
2022-06-10 16:07 ` [PULL 07/28] target/arm: Move exception_bkpt_insn to debug_helper.c Peter Maydell
2022-06-10 16:07 ` [PULL 08/28] target/arm: Move arm_debug_exception_fsr " Peter Maydell
2022-06-10 16:07 ` [PULL 09/28] target/arm: Rename helper_exception_with_syndrome Peter Maydell
2022-06-10 16:07 ` [PULL 10/28] target/arm: Introduce gen_exception_insn_el_v Peter Maydell
2022-06-10 16:07 ` [PULL 11/28] target/arm: Rename gen_exception_insn to gen_exception_insn_el Peter Maydell
2022-06-10 16:07 ` [PULL 12/28] target/arm: Introduce gen_exception_insn Peter Maydell
2022-06-10 16:07 ` [PULL 13/28] target/arm: Create helper_exception_swstep Peter Maydell
2022-06-10 16:07 ` [PULL 14/28] target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_EL Peter Maydell
2022-06-10 16:07 ` [PULL 15/28] target/arm: Move gen_exception to translate.c Peter Maydell
2022-06-10 16:07 ` [PULL 16/28] target/arm: Rename gen_exception to gen_exception_el Peter Maydell
2022-06-10 16:07 ` [PULL 17/28] target/arm: Introduce gen_exception Peter Maydell
2022-06-10 16:07 ` [PULL 18/28] target/arm: Introduce gen_exception_el_v Peter Maydell
2022-06-10 16:07 ` Peter Maydell [this message]
2022-06-10 16:07 ` [PULL 20/28] target/arm: Remove default_exception_el Peter Maydell
2022-06-10 16:07 ` [PULL 21/28] target/arm: Create raise_exception_debug Peter Maydell
2022-06-10 16:07 ` [PULL 22/28] target/arm: Move arm_debug_target_el to debug_helper.c Peter Maydell
2022-06-10 16:07 ` [PULL 23/28] target/arm: Fix Secure PL1 tests in fp_exception_el Peter Maydell
2022-06-10 16:07 ` [PULL 24/28] tests/qtest: Reduce npcm7xx_sdhci test image size Peter Maydell
2022-06-10 16:07 ` [PULL 25/28] target/arm: Adjust format test in scr_write Peter Maydell
2022-06-10 16:07 ` [PULL 26/28] target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12] Peter Maydell
2022-06-10 16:07 ` [PULL 27/28] gdbstub: Don't use GDB syscalls if no GDB is attached Peter Maydell
2022-06-10 16:07 ` [PULL 28/28] semihosting/config: Merge --semihosting-config option groups Peter Maydell
2022-06-10 23:10 ` [PULL 00/28] target-arm queue Richard Henderson

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