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From: Christoph Hellwig <hch@lst.de>
To: Samuel Holland <samuel@sholland.org>
Cc: Heiko Stuebner <heiko@sntech.de>,
	palmer@dabbelt.com, paul.walmsley@sifive.com,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	wefu@redhat.com, guoren@kernel.org, cmuellner@linux.com,
	philipp.tomsich@vrull.eu, hch@lst.de, atishp@atishpatra.org,
	anup@brainfault.org, mick@ics.forth.gr, robh+dt@kernel.org,
	krzk+dt@kernel.org, devicetree@vger.kernel.org,
	drew@beagleboard.org, Atish Patra <atish.patra@wdc.com>
Subject: Re: [PATCH 2/3] riscv: Implement Zicbom-based cache management operations
Date: Mon, 13 Jun 2022 07:50:29 +0200	[thread overview]
Message-ID: <20220613055029.GA32155@lst.de> (raw)
In-Reply-To: <342e3c12-ebb0-badf-7d4c-c444a2b842b2@sholland.org>

On Sun, Jun 12, 2022 at 02:15:00PM -0500, Samuel Holland wrote:
> > +config RISCV_ISA_ZICBOM
> > +	bool "Zicbom extension support for non-coherent dma operation"
> > +	select ARCH_HAS_DMA_PREP_COHERENT
> > +	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
> > +	select ARCH_HAS_SYNC_DMA_FOR_CPU
> > +	select ARCH_HAS_SETUP_DMA_OPS
> 
> ARCH_HAS_SETUP_DMA_OPS needs to be separate from the non-coherent DMA option,
> because iommu_setup_dma_ops() will need to be called from arch_setup_dma_ops()
> even on a fully-coherent system. (But this change is not strictly necessary for
> this series.)

It doesn't need to be separate, you can just add another select for
the symbol.

> > +	case DMA_FROM_DEVICE:
> > +		ALT_CMO_OP(INVAL, (unsigned long)phys_to_virt(paddr), size, riscv_cbom_block_size);
> > +		break;
> 
> arch_sync_dma_for_device(DMA_FROM_DEVICE) is a no-op from the CPU's perspective.
> Invalidating the CPU's cache goes in arch_sync_dma_for_cpu(DMA_FROM_DEVICE).

Only if you guarantee that there is never any speculation.  See:

https://lore.kernel.org/lkml/20180518175004.GF17671@n2100.armlinux.org.uk

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WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: Samuel Holland <samuel@sholland.org>
Cc: Heiko Stuebner <heiko@sntech.de>,
	palmer@dabbelt.com, paul.walmsley@sifive.com,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	wefu@redhat.com, guoren@kernel.org, cmuellner@linux.com,
	philipp.tomsich@vrull.eu, hch@lst.de, atishp@atishpatra.org,
	anup@brainfault.org, mick@ics.forth.gr, robh+dt@kernel.org,
	krzk+dt@kernel.org, devicetree@vger.kernel.org,
	drew@beagleboard.org, Atish Patra <atish.patra@wdc.com>
Subject: Re: [PATCH 2/3] riscv: Implement Zicbom-based cache management operations
Date: Mon, 13 Jun 2022 07:50:29 +0200	[thread overview]
Message-ID: <20220613055029.GA32155@lst.de> (raw)
In-Reply-To: <342e3c12-ebb0-badf-7d4c-c444a2b842b2@sholland.org>

On Sun, Jun 12, 2022 at 02:15:00PM -0500, Samuel Holland wrote:
> > +config RISCV_ISA_ZICBOM
> > +	bool "Zicbom extension support for non-coherent dma operation"
> > +	select ARCH_HAS_DMA_PREP_COHERENT
> > +	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
> > +	select ARCH_HAS_SYNC_DMA_FOR_CPU
> > +	select ARCH_HAS_SETUP_DMA_OPS
> 
> ARCH_HAS_SETUP_DMA_OPS needs to be separate from the non-coherent DMA option,
> because iommu_setup_dma_ops() will need to be called from arch_setup_dma_ops()
> even on a fully-coherent system. (But this change is not strictly necessary for
> this series.)

It doesn't need to be separate, you can just add another select for
the symbol.

> > +	case DMA_FROM_DEVICE:
> > +		ALT_CMO_OP(INVAL, (unsigned long)phys_to_virt(paddr), size, riscv_cbom_block_size);
> > +		break;
> 
> arch_sync_dma_for_device(DMA_FROM_DEVICE) is a no-op from the CPU's perspective.
> Invalidating the CPU's cache goes in arch_sync_dma_for_cpu(DMA_FROM_DEVICE).

Only if you guarantee that there is never any speculation.  See:

https://lore.kernel.org/lkml/20180518175004.GF17671@n2100.armlinux.org.uk

  reply	other threads:[~2022-06-13  5:50 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-10  0:43 [PATCH v3 0/3] riscv: implement Zicbom-based CMO instructions + the t-head variant Heiko Stuebner
2022-06-10  0:43 ` Heiko Stuebner
2022-06-10  0:43 ` [PATCH 1/3] dt-bindings: riscv: document cbom-block-size Heiko Stuebner
2022-06-10  0:43   ` Heiko Stuebner
2022-06-17 20:37   ` Rob Herring
2022-06-17 20:37     ` Rob Herring
2022-06-10  0:43 ` [PATCH 2/3] riscv: Implement Zicbom-based cache management operations Heiko Stuebner
2022-06-10  0:43   ` Heiko Stuebner
2022-06-10  3:22   ` Randy Dunlap
2022-06-10  3:22     ` Randy Dunlap
2022-06-10  5:56   ` Christoph Hellwig
2022-06-10  5:56     ` Christoph Hellwig
2022-06-15 16:56     ` Heiko Stübner
2022-06-15 16:56       ` Heiko Stübner
2022-06-15 17:49       ` Christoph Hellwig
2022-06-15 17:49         ` Christoph Hellwig
2022-06-16  9:46         ` Heiko Stübner
2022-06-16  9:46           ` Heiko Stübner
2022-06-16 11:53           ` Christoph Hellwig
2022-06-16 11:53             ` Christoph Hellwig
2022-06-16 12:09             ` Heiko Stübner
2022-06-16 12:09               ` Heiko Stübner
2022-06-16 12:11               ` Christoph Hellwig
2022-06-16 12:11                 ` Christoph Hellwig
2022-06-17  8:30                 ` Heiko Stübner
2022-06-17  8:30                   ` Heiko Stübner
2022-06-12 19:15   ` Samuel Holland
2022-06-12 19:15     ` Samuel Holland
2022-06-13  5:50     ` Christoph Hellwig [this message]
2022-06-13  5:50       ` Christoph Hellwig
2022-06-10  0:43 ` [PATCH 3/3] riscv: implement cache-management errata for T-Head SoCs Heiko Stuebner
2022-06-10  0:43   ` Heiko Stuebner
2022-06-10  1:04   ` Guo Ren
2022-06-10  1:04     ` Guo Ren
2022-06-12 19:18   ` Samuel Holland
2022-06-12 19:18     ` Samuel Holland

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