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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230016)(4636009)(46966006)(40470700004)(36840700001)(66574015)(40460700003)(26005)(2906002)(7696005)(36756003)(47076005)(336012)(7416002)(426003)(6916009)(81166007)(36860700001)(316002)(16526019)(6666004)(83380400001)(186003)(82310400005)(19273905006)(8936002)(30864003)(86362001)(4326008)(70586007)(356005)(8676002)(2616005)(70206006)(54906003)(508600001)(5660300002)(1076003)(36900700001)(579004)(559001)(563064011); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jun 2022 20:01:54.2629 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f4b05fb-ea0c-4a2e-13fd-08da4d77904a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4545 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Pierre-Eric Pelloux-Prayer , Mark Yacoub , Pekka Paalanen , Simon Ser , =?UTF-8?q?Michel=20D=C3=A4nzer?= , Alex Hung , maira.canal@usp.br, mwen@igalia.com, Leo Li , Bhawanpreet Lakha , Hersen Wu , tales.aparecida@gmail.com, Sean Paul , isabbasso@riseup.net, andrealmeid@riseup.net, Harry Wentland , Nicholas Kazlauskas , Pierre-Loup Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" In the DCN code, we constantly talk about hardware pipeline, pipeline, or even just pipes, which is a concept that is not obvious to everyone. For this reason, this commit expands the DCN overview explanation by adding a new section that describes what a pipeline is from the DCN perspective. Cc: Harry Wentland Cc: Nicholas Kazlauskas Cc: Bhawanpreet Lakha Cc: Hersen Wu Cc: Alex Hung Cc: Pierre-Eric Pelloux-Prayer Cc: Leo Li Cc: Simon Ser Cc: Pekka Paalanen Cc: Sean Paul Cc: Mark Yacoub Cc: Pierre-Loup Cc: Michel Dänzer Signed-off-by: Rodrigo Siqueira --- .../gpu/amdgpu/display/dcn-overview.rst | 58 + .../amdgpu/display/pipeline_4k_no_split.svg | 958 +++++++++++++++ .../gpu/amdgpu/display/pipeline_4k_split.svg | 1062 +++++++++++++++++ 3 files changed, 2078 insertions(+) create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_split.svg diff --git a/Documentation/gpu/amdgpu/display/dcn-overview.rst b/Documentation/gpu/amdgpu/display/dcn-overview.rst index f98624d7828e..430e363fccae 100644 --- a/Documentation/gpu/amdgpu/display/dcn-overview.rst +++ b/Documentation/gpu/amdgpu/display/dcn-overview.rst @@ -124,6 +124,64 @@ depth format), bit-depth reduction/dithering would kick in. In OPP, we would also apply a regamma function to introduce the gamma removed earlier back. Eventually, we output data in integer format at DIO. +AMD Hardware Pipeline +--------------------- + +When discussing graphics on Linux, the **pipeline** term is often overloaded +with multiple meanings, and DCN adds another context to this word. In the DCN +driver, we use the term **hardware pipeline** or **pipeline** or just **pipe** +to indicate how many DCN blocks we are instantiating to address some specific +configuration. DCN composes those pipelines together when the data reach the +end of the OPTC block before sending it to the display. We have this pipeline +concept for trying to save energy and optimize bandwidth utilization while +providing the maximum performance per watt. It is easier to discuss it if we +dive into this topic by taking the example of a 4k display in the below +example: + +.. kernel-figure:: pipeline_4k_no_split.svg + +Additionally, let's take a look at parts of the DTN log (see +'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since +this log can help us to see part of this pipeline behavior in real-time:: + + HUBP: format addr_hi width height ... + [ 0]: 8h 81h 3840 2160 + [ 1]: 0h 0h 0 0 + [ 2]: 0h 0h 0 0 + [ 3]: 0h 0h 0 0 + [ 4]: 0h 0h 0 0 + ... + MPCC: OPP DPP ... + [ 0]: 0h 0h ... + +The first thing to notice from the diagram and DTN log it is the fact that we +have different clock domains for each part of the DCN blocks. In this example, +we have just a single **pipeline** where the data flows from DCHUB to DIO, as +we intuitively expect. Nonetheless, DCN is flexible, as mentioned before, and +we can split this single pipe differently, as described in the below diagram: + +.. kernel-figure:: pipeline_4k_split.svg + +Now, if we inspect the DTN log again we can see some interesting changes:: + + HUBP: format addr_hi width height ... + [ 0]: 8h 81h 1920 2160 ... + ... + [ 4]: 0h 0h 0 0 ... + [ 5]: 8h 81h 1920 2160 ... + ... + MPCC: OPP DPP ... + [ 0]: 0h 0h ... + [ 5]: 0h 5h ... + +From the above example, we now split the display pipeline into two vertical +parts of 1920x2160 (i.e., 3440x2160), and as a result, we could reduce the +clock frequency in the DPP part. This is not only useful for saving power but +also to better handle the required throughput. The idea to keep in mind here is +that the pipe configuration can vary a lot according to the display +configuration, and it is the DML's responsibility to set up all required +configuration parameters for multiple scenarios supported by our hardware. + Global Sync ----------- diff --git a/Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg b/Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg new file mode 100644 index 000000000000..5fa289d99fcd --- /dev/null +++ b/Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg @@ -0,0 +1,958 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + DCHUB + + DPP(0) + + + + + HUBP(0) + + + + + + HUBP(1) + + + + + + HUBP(5) + + + + + ... + + ... + + + MPC(0) + + + + OPP(0) + + + ... + + + + OPTC + + + + ... + + SDP + + + + DPPCLK535.916Mhz + DISPCLK541.275 Mhz + DCFCLK506 Mhz + SymCLK + + DIO + + + + VirtualPCLK + + + diff --git a/Documentation/gpu/amdgpu/display/pipeline_4k_split.svg b/Documentation/gpu/amdgpu/display/pipeline_4k_split.svg new file mode 100644 index 000000000000..b43119e7eb8a --- /dev/null +++ b/Documentation/gpu/amdgpu/display/pipeline_4k_split.svg @@ -0,0 +1,1062 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + DCHUB + + DPP(0) + + + + + HUBP(0) + + + + + + HUBP(1) + + + + + + HUBP(5) + + + + + ... + + DPP(5) + + + + + ... + + + MPC(0) + + + + MPC(5) + + + + OPP(0) + + + ... + + + + + OPP(0) + + + + + OPTC + + + + + ... + + SDP + + + + DPPCLK267.958Mhz + DISPCLK541.275 Mhz + DCFCLK506 Mhz + SymCLK + + DIO + + + + VirtualPCLK + + + -- 2.25.1