From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EEC5CCA473 for ; Wed, 15 Jun 2022 17:11:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349893AbiFORLi (ORCPT ); Wed, 15 Jun 2022 13:11:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356695AbiFORLf (ORCPT ); Wed, 15 Jun 2022 13:11:35 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A08FA5005B; Wed, 15 Jun 2022 10:11:34 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3131A61A21; Wed, 15 Jun 2022 17:11:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 30837C34115; Wed, 15 Jun 2022 17:11:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655313093; bh=2QTNhmLA5hWHCcKhZRTumnrveKImZcwK8CtdtQayAoE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=pItRVJvXT15nVht43ZGZHiEklBwD3Dvjt2Adm2xDW4d9yp44MRNlmnHiHjI166/w/ hRl9XV3mOLBAyiAszzUq5o/b9vPFyJLLChpGM4RrxBbkBZLUE+mtiGuLt+k3Fq3ayi 3cZHD50b4hrMk5vZ5JAGloUAD1I4QWoArrwzYACVlkUmmMYdfb96ce5rBJBD7rJTNn EC3DO9LkVd8pUEbTyWav9RIdXmd3neATi9gp5u80F/ShD+NQDQ7snNZVGm2JvNdxrQ 7RHir6gCRUGGp6T+yv2E59dw/SQnSmHFLDJgqlVmxRAnCfnTpLrORnJqz6cKgY4NdZ zQb7oIxHiZjfg== Date: Wed, 15 Jun 2022 22:41:32 +0530 From: Manivannan Sadhasivam To: Ansuel Smith Cc: Andy Gross , Bjorn Andersson , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v7 1/3] mtd: nand: raw: qcom_nandc: reorder qcom_nand_host struct Message-ID: <20220615171132.GA3606@thinkpad> References: <20220615000612.3119-1-ansuelsmth@gmail.com> <20220615000612.3119-2-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220615000612.3119-2-ansuelsmth@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed, Jun 15, 2022 at 02:06:10AM +0200, Ansuel Smith wrote: > Reorder structs in nandc driver to save holes. > > Signed-off-by: Ansuel Smith Reviewed-by: Manivannan Sadhasivam Thanks, Mani > --- > drivers/mtd/nand/raw/qcom_nandc.c | 107 +++++++++++++++++------------- > 1 file changed, 62 insertions(+), 45 deletions(-) > > diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c > index 1a77542c6d67..f2990d721733 100644 > --- a/drivers/mtd/nand/raw/qcom_nandc.c > +++ b/drivers/mtd/nand/raw/qcom_nandc.c > @@ -238,6 +238,9 @@ nandc_set_reg(chip, reg, \ > * @bam_ce - the array of BAM command elements > * @cmd_sgl - sgl for NAND BAM command pipe > * @data_sgl - sgl for NAND BAM consumer/producer pipe > + * @last_data_desc - last DMA desc in data channel (tx/rx). > + * @last_cmd_desc - last DMA desc in command channel. > + * @txn_done - completion for NAND transfer. > * @bam_ce_pos - the index in bam_ce which is available for next sgl > * @bam_ce_start - the index in bam_ce which marks the start position ce > * for current sgl. It will be used for size calculation > @@ -250,14 +253,14 @@ nandc_set_reg(chip, reg, \ > * @rx_sgl_start - start index in data sgl for rx. > * @wait_second_completion - wait for second DMA desc completion before making > * the NAND transfer completion. > - * @txn_done - completion for NAND transfer. > - * @last_data_desc - last DMA desc in data channel (tx/rx). > - * @last_cmd_desc - last DMA desc in command channel. > */ > struct bam_transaction { > struct bam_cmd_element *bam_ce; > struct scatterlist *cmd_sgl; > struct scatterlist *data_sgl; > + struct dma_async_tx_descriptor *last_data_desc; > + struct dma_async_tx_descriptor *last_cmd_desc; > + struct completion txn_done; > u32 bam_ce_pos; > u32 bam_ce_start; > u32 cmd_sgl_pos; > @@ -267,25 +270,23 @@ struct bam_transaction { > u32 rx_sgl_pos; > u32 rx_sgl_start; > bool wait_second_completion; > - struct completion txn_done; > - struct dma_async_tx_descriptor *last_data_desc; > - struct dma_async_tx_descriptor *last_cmd_desc; > }; > > /* > * This data type corresponds to the nand dma descriptor > + * @dma_desc - low level DMA engine descriptor > * @list - list for desc_info > - * @dir - DMA transfer direction > + * > * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by > * ADM > * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM > * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM > - * @dma_desc - low level DMA engine descriptor > + * @dir - DMA transfer direction > */ > struct desc_info { > + struct dma_async_tx_descriptor *dma_desc; > struct list_head node; > > - enum dma_data_direction dir; > union { > struct scatterlist adm_sgl; > struct { > @@ -293,7 +294,7 @@ struct desc_info { > int sgl_cnt; > }; > }; > - struct dma_async_tx_descriptor *dma_desc; > + enum dma_data_direction dir; > }; > > /* > @@ -337,52 +338,64 @@ struct nandc_regs { > /* > * NAND controller data struct > * > - * @controller: base controller structure > - * @host_list: list containing all the chips attached to the > - * controller > * @dev: parent device > + * > * @base: MMIO base > - * @base_phys: physical base address of controller registers > - * @base_dma: dma base address of controller registers > + * > * @core_clk: controller clock > * @aon_clk: another controller clock > * > + * @regs: a contiguous chunk of memory for DMA register > + * writes. contains the register values to be > + * written to controller > + * > + * @props: properties of current NAND controller, > + * initialized via DT match data > + * > + * @controller: base controller structure > + * @host_list: list containing all the chips attached to the > + * controller > + * > * @chan: dma channel > * @cmd_crci: ADM DMA CRCI for command flow control > * @data_crci: ADM DMA CRCI for data flow control > + * > * @desc_list: DMA descriptor list (list of desc_infos) > * > * @data_buffer: our local DMA buffer for page read/writes, > * used when we can't use the buffer provided > * by upper layers directly > - * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf > - * functions > * @reg_read_buf: local buffer for reading back registers via DMA > + * > + * @base_phys: physical base address of controller registers > + * @base_dma: dma base address of controller registers > * @reg_read_dma: contains dma address for register read buffer > - * @reg_read_pos: marker for data read in reg_read_buf > * > - * @regs: a contiguous chunk of memory for DMA register > - * writes. contains the register values to be > - * written to controller > - * @cmd1/vld: some fixed controller register values > - * @props: properties of current NAND controller, > - * initialized via DT match data > + * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf > + * functions > * @max_cwperpage: maximum QPIC codewords required. calculated > * from all connected NAND devices pagesize > + * > + * @reg_read_pos: marker for data read in reg_read_buf > + * > + * @cmd1/vld: some fixed controller register values > */ > struct qcom_nand_controller { > - struct nand_controller controller; > - struct list_head host_list; > - > struct device *dev; > > void __iomem *base; > - phys_addr_t base_phys; > - dma_addr_t base_dma; > > struct clk *core_clk; > struct clk *aon_clk; > > + struct nandc_regs *regs; > + struct bam_transaction *bam_txn; > + > + const struct qcom_nandc_props *props; > + > + struct nand_controller controller; > + struct list_head host_list; > + > union { > /* will be used only by QPIC for BAM DMA */ > struct { > @@ -400,22 +413,22 @@ struct qcom_nand_controller { > }; > > struct list_head desc_list; > - struct bam_transaction *bam_txn; > > u8 *data_buffer; > + __le32 *reg_read_buf; > + > + phys_addr_t base_phys; > + dma_addr_t base_dma; > + dma_addr_t reg_read_dma; > + > int buf_size; > int buf_count; > int buf_start; > unsigned int max_cwperpage; > > - __le32 *reg_read_buf; > - dma_addr_t reg_read_dma; > int reg_read_pos; > > - struct nandc_regs *regs; > - > u32 cmd1, vld; > - const struct qcom_nandc_props *props; > }; > > /* > @@ -431,19 +444,21 @@ struct qcom_nand_controller { > * and reserved bytes > * @cw_data: the number of bytes within a codeword protected > * by ECC > - * @use_ecc: request the controller to use ECC for the > - * upcoming read/write > - * @bch_enabled: flag to tell whether BCH ECC mode is used > * @ecc_bytes_hw: ECC bytes used by controller hardware for this > * chip > - * @status: value to be returned if NAND_CMD_STATUS command > - * is executed > + * > * @last_command: keeps track of last command on this chip. used > * for reading correct status > * > * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for > * ecc/non-ecc mode for the current nand flash > * device > + * > + * @status: value to be returned if NAND_CMD_STATUS command > + * is executed > + * @use_ecc: request the controller to use ECC for the > + * upcoming read/write > + * @bch_enabled: flag to tell whether BCH ECC mode is used > */ > struct qcom_nand_host { > struct nand_chip chip; > @@ -452,12 +467,10 @@ struct qcom_nand_host { > int cs; > int cw_size; > int cw_data; > - bool use_ecc; > - bool bch_enabled; > int ecc_bytes_hw; > int spare_bytes; > int bbm_size; > - u8 status; > + > int last_command; > > u32 cfg0, cfg1; > @@ -466,23 +479,27 @@ struct qcom_nand_host { > u32 ecc_bch_cfg; > u32 clrflashstatus; > u32 clrreadstatus; > + > + u8 status; > + bool use_ecc; > + bool bch_enabled; > }; > > /* > * This data type corresponds to the NAND controller properties which varies > * among different NAND controllers. > * @ecc_modes - ecc mode for NAND > + * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset > * @is_bam - whether NAND controller is using BAM > * @is_qpic - whether NAND CTRL is part of qpic IP > * @qpic_v2 - flag to indicate QPIC IP version 2 > - * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset > */ > struct qcom_nandc_props { > u32 ecc_modes; > + u32 dev_cmd_reg_start; > bool is_bam; > bool is_qpic; > bool qpic_v2; > - u32 dev_cmd_reg_start; > }; > > /* Frees the BAM transaction memory */ > -- > 2.36.1 > -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D6D0C433EF for ; Wed, 15 Jun 2022 17:11:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=f9HMhxT8+oYS5owIoMpC/25pKiUT2SSdNQalNjCdITE=; b=fZkGlC3DGfBbK9 0CDgE141zU2QhqWZX9aBCN605Rzhd29HJOD8A7tInawRw3ftEcPL/n5hJrJFfeYG0ska+tPDacwbW SEvaLENgUFIjsIQIaHgvn+Ku4ip0FqzG3ATNoEosDw7qq6tO9wDhx33+ktnACBdkGhoNsTKihLwUA gB0I1RvC2jYALRp8FyOLjlf5i9EZ7Pci/Mlu1W9263xJ1VxRJRXimgkO1B1hlzZ46BdHeO1J8lqKw 7rMEmUwBxqPLKZUtGNPTKYqnsgUvwVtaEpOiOJuKDPvpUtujnWYzK10Kh0TiuQhx051SqS4l4XOts +Z161OzS+Uaw6q5/yGpw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o1WYO-00FbmO-8m; Wed, 15 Jun 2022 17:11:40 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o1WYK-00Fbkw-Il for linux-mtd@lists.infradead.org; Wed, 15 Jun 2022 17:11:38 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 0DF38B81FF0; Wed, 15 Jun 2022 17:11:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 30837C34115; Wed, 15 Jun 2022 17:11:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655313093; bh=2QTNhmLA5hWHCcKhZRTumnrveKImZcwK8CtdtQayAoE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=pItRVJvXT15nVht43ZGZHiEklBwD3Dvjt2Adm2xDW4d9yp44MRNlmnHiHjI166/w/ hRl9XV3mOLBAyiAszzUq5o/b9vPFyJLLChpGM4RrxBbkBZLUE+mtiGuLt+k3Fq3ayi 3cZHD50b4hrMk5vZ5JAGloUAD1I4QWoArrwzYACVlkUmmMYdfb96ce5rBJBD7rJTNn EC3DO9LkVd8pUEbTyWav9RIdXmd3neATi9gp5u80F/ShD+NQDQ7snNZVGm2JvNdxrQ 7RHir6gCRUGGp6T+yv2E59dw/SQnSmHFLDJgqlVmxRAnCfnTpLrORnJqz6cKgY4NdZ zQb7oIxHiZjfg== Date: Wed, 15 Jun 2022 22:41:32 +0530 From: Manivannan Sadhasivam To: Ansuel Smith Cc: Andy Gross , Bjorn Andersson , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v7 1/3] mtd: nand: raw: qcom_nandc: reorder qcom_nand_host struct Message-ID: <20220615171132.GA3606@thinkpad> References: <20220615000612.3119-1-ansuelsmth@gmail.com> <20220615000612.3119-2-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220615000612.3119-2-ansuelsmth@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220615_101136_981766_47D38D9F X-CRM114-Status: GOOD ( 35.18 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org T24gV2VkLCBKdW4gMTUsIDIwMjIgYXQgMDI6MDY6MTBBTSArMDIwMCwgQW5zdWVsIFNtaXRoIHdy b3RlOgo+IFJlb3JkZXIgc3RydWN0cyBpbiBuYW5kYyBkcml2ZXIgdG8gc2F2ZSBob2xlcy4KPiAK PiBTaWduZWQtb2ZmLWJ5OiBBbnN1ZWwgU21pdGggPGFuc3VlbHNtdGhAZ21haWwuY29tPgoKUmV2 aWV3ZWQtYnk6IE1hbml2YW5uYW4gU2FkaGFzaXZhbSA8bWFuaUBrZXJuZWwub3JnPgoKVGhhbmtz LApNYW5pCgo+IC0tLQo+ICBkcml2ZXJzL210ZC9uYW5kL3Jhdy9xY29tX25hbmRjLmMgfCAxMDcg KysrKysrKysrKysrKysrKystLS0tLS0tLS0tLS0tCj4gIDEgZmlsZSBjaGFuZ2VkLCA2MiBpbnNl cnRpb25zKCspLCA0NSBkZWxldGlvbnMoLSkKPiAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9tdGQv bmFuZC9yYXcvcWNvbV9uYW5kYy5jIGIvZHJpdmVycy9tdGQvbmFuZC9yYXcvcWNvbV9uYW5kYy5j Cj4gaW5kZXggMWE3NzU0MmM2ZDY3Li5mMjk5MGQ3MjE3MzMgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVy cy9tdGQvbmFuZC9yYXcvcWNvbV9uYW5kYy5jCj4gKysrIGIvZHJpdmVycy9tdGQvbmFuZC9yYXcv cWNvbV9uYW5kYy5jCj4gQEAgLTIzOCw2ICsyMzgsOSBAQCBuYW5kY19zZXRfcmVnKGNoaXAsIHJl ZywJCQlcCj4gICAqIEBiYW1fY2UgLSB0aGUgYXJyYXkgb2YgQkFNIGNvbW1hbmQgZWxlbWVudHMK PiAgICogQGNtZF9zZ2wgLSBzZ2wgZm9yIE5BTkQgQkFNIGNvbW1hbmQgcGlwZQo+ICAgKiBAZGF0 YV9zZ2wgLSBzZ2wgZm9yIE5BTkQgQkFNIGNvbnN1bWVyL3Byb2R1Y2VyIHBpcGUKPiArICogQGxh c3RfZGF0YV9kZXNjIC0gbGFzdCBETUEgZGVzYyBpbiBkYXRhIGNoYW5uZWwgKHR4L3J4KS4KPiAr ICogQGxhc3RfY21kX2Rlc2MgLSBsYXN0IERNQSBkZXNjIGluIGNvbW1hbmQgY2hhbm5lbC4KPiAr ICogQHR4bl9kb25lIC0gY29tcGxldGlvbiBmb3IgTkFORCB0cmFuc2Zlci4KPiAgICogQGJhbV9j ZV9wb3MgLSB0aGUgaW5kZXggaW4gYmFtX2NlIHdoaWNoIGlzIGF2YWlsYWJsZSBmb3IgbmV4dCBz Z2wKPiAgICogQGJhbV9jZV9zdGFydCAtIHRoZSBpbmRleCBpbiBiYW1fY2Ugd2hpY2ggbWFya3Mg dGhlIHN0YXJ0IHBvc2l0aW9uIGNlCj4gICAqCQkgICBmb3IgY3VycmVudCBzZ2wuIEl0IHdpbGwg YmUgdXNlZCBmb3Igc2l6ZSBjYWxjdWxhdGlvbgo+IEBAIC0yNTAsMTQgKzI1MywxNCBAQCBuYW5k Y19zZXRfcmVnKGNoaXAsIHJlZywJCQlcCj4gICAqIEByeF9zZ2xfc3RhcnQgLSBzdGFydCBpbmRl eCBpbiBkYXRhIHNnbCBmb3IgcnguCj4gICAqIEB3YWl0X3NlY29uZF9jb21wbGV0aW9uIC0gd2Fp dCBmb3Igc2Vjb25kIERNQSBkZXNjIGNvbXBsZXRpb24gYmVmb3JlIG1ha2luZwo+ICAgKgkJCSAg ICAgdGhlIE5BTkQgdHJhbnNmZXIgY29tcGxldGlvbi4KPiAtICogQHR4bl9kb25lIC0gY29tcGxl dGlvbiBmb3IgTkFORCB0cmFuc2Zlci4KPiAtICogQGxhc3RfZGF0YV9kZXNjIC0gbGFzdCBETUEg ZGVzYyBpbiBkYXRhIGNoYW5uZWwgKHR4L3J4KS4KPiAtICogQGxhc3RfY21kX2Rlc2MgLSBsYXN0 IERNQSBkZXNjIGluIGNvbW1hbmQgY2hhbm5lbC4KPiAgICovCj4gIHN0cnVjdCBiYW1fdHJhbnNh Y3Rpb24gewo+ICAJc3RydWN0IGJhbV9jbWRfZWxlbWVudCAqYmFtX2NlOwo+ICAJc3RydWN0IHNj YXR0ZXJsaXN0ICpjbWRfc2dsOwo+ICAJc3RydWN0IHNjYXR0ZXJsaXN0ICpkYXRhX3NnbDsKPiAr CXN0cnVjdCBkbWFfYXN5bmNfdHhfZGVzY3JpcHRvciAqbGFzdF9kYXRhX2Rlc2M7Cj4gKwlzdHJ1 Y3QgZG1hX2FzeW5jX3R4X2Rlc2NyaXB0b3IgKmxhc3RfY21kX2Rlc2M7Cj4gKwlzdHJ1Y3QgY29t cGxldGlvbiB0eG5fZG9uZTsKPiAgCXUzMiBiYW1fY2VfcG9zOwo+ICAJdTMyIGJhbV9jZV9zdGFy dDsKPiAgCXUzMiBjbWRfc2dsX3BvczsKPiBAQCAtMjY3LDI1ICsyNzAsMjMgQEAgc3RydWN0IGJh bV90cmFuc2FjdGlvbiB7Cj4gIAl1MzIgcnhfc2dsX3BvczsKPiAgCXUzMiByeF9zZ2xfc3RhcnQ7 Cj4gIAlib29sIHdhaXRfc2Vjb25kX2NvbXBsZXRpb247Cj4gLQlzdHJ1Y3QgY29tcGxldGlvbiB0 eG5fZG9uZTsKPiAtCXN0cnVjdCBkbWFfYXN5bmNfdHhfZGVzY3JpcHRvciAqbGFzdF9kYXRhX2Rl c2M7Cj4gLQlzdHJ1Y3QgZG1hX2FzeW5jX3R4X2Rlc2NyaXB0b3IgKmxhc3RfY21kX2Rlc2M7Cj4g IH07Cj4gIAo+ICAvKgo+ICAgKiBUaGlzIGRhdGEgdHlwZSBjb3JyZXNwb25kcyB0byB0aGUgbmFu ZCBkbWEgZGVzY3JpcHRvcgo+ICsgKiBAZG1hX2Rlc2MgLSBsb3cgbGV2ZWwgRE1BIGVuZ2luZSBk ZXNjcmlwdG9yCj4gICAqIEBsaXN0IC0gbGlzdCBmb3IgZGVzY19pbmZvCj4gLSAqIEBkaXIgLSBE TUEgdHJhbnNmZXIgZGlyZWN0aW9uCj4gKyAqCj4gICAqIEBhZG1fc2dsIC0gc2dsIHdoaWNoIHdp bGwgYmUgdXNlZCBmb3Igc2luZ2xlIHNnbCBkbWEgZGVzY3JpcHRvci4gT25seSB1c2VkIGJ5Cj4g ICAqCSAgICAgIEFETQo+ICAgKiBAYmFtX3NnbCAtIHNnbCB3aGljaCB3aWxsIGJlIHVzZWQgZm9y IGRtYSBkZXNjcmlwdG9yLiBPbmx5IHVzZWQgYnkgQkFNCj4gICAqIEBzZ2xfY250IC0gbnVtYmVy IG9mIFNHTCBpbiBiYW1fc2dsLiBPbmx5IHVzZWQgYnkgQkFNCj4gLSAqIEBkbWFfZGVzYyAtIGxv dyBsZXZlbCBETUEgZW5naW5lIGRlc2NyaXB0b3IKPiArICogQGRpciAtIERNQSB0cmFuc2ZlciBk aXJlY3Rpb24KPiAgICovCj4gIHN0cnVjdCBkZXNjX2luZm8gewo+ICsJc3RydWN0IGRtYV9hc3lu Y190eF9kZXNjcmlwdG9yICpkbWFfZGVzYzsKPiAgCXN0cnVjdCBsaXN0X2hlYWQgbm9kZTsKPiAg Cj4gLQllbnVtIGRtYV9kYXRhX2RpcmVjdGlvbiBkaXI7Cj4gIAl1bmlvbiB7Cj4gIAkJc3RydWN0 IHNjYXR0ZXJsaXN0IGFkbV9zZ2w7Cj4gIAkJc3RydWN0IHsKPiBAQCAtMjkzLDcgKzI5NCw3IEBA IHN0cnVjdCBkZXNjX2luZm8gewo+ICAJCQlpbnQgc2dsX2NudDsKPiAgCQl9Owo+ICAJfTsKPiAt CXN0cnVjdCBkbWFfYXN5bmNfdHhfZGVzY3JpcHRvciAqZG1hX2Rlc2M7Cj4gKwllbnVtIGRtYV9k YXRhX2RpcmVjdGlvbiBkaXI7Cj4gIH07Cj4gIAo+ICAvKgo+IEBAIC0zMzcsNTIgKzMzOCw2NCBA QCBzdHJ1Y3QgbmFuZGNfcmVncyB7Cj4gIC8qCj4gICAqIE5BTkQgY29udHJvbGxlciBkYXRhIHN0 cnVjdAo+ICAgKgo+IC0gKiBAY29udHJvbGxlcjoJCQliYXNlIGNvbnRyb2xsZXIgc3RydWN0dXJl Cj4gLSAqIEBob3N0X2xpc3Q6CQkJbGlzdCBjb250YWluaW5nIGFsbCB0aGUgY2hpcHMgYXR0YWNo ZWQgdG8gdGhlCj4gLSAqCQkJCWNvbnRyb2xsZXIKPiAgICogQGRldjoJCQlwYXJlbnQgZGV2aWNl Cj4gKyAqCj4gICAqIEBiYXNlOgkJCU1NSU8gYmFzZQo+IC0gKiBAYmFzZV9waHlzOgkJCXBoeXNp Y2FsIGJhc2UgYWRkcmVzcyBvZiBjb250cm9sbGVyIHJlZ2lzdGVycwo+IC0gKiBAYmFzZV9kbWE6 CQkJZG1hIGJhc2UgYWRkcmVzcyBvZiBjb250cm9sbGVyIHJlZ2lzdGVycwo+ICsgKgo+ICAgKiBA Y29yZV9jbGs6CQkJY29udHJvbGxlciBjbG9jawo+ICAgKiBAYW9uX2NsazoJCQlhbm90aGVyIGNv bnRyb2xsZXIgY2xvY2sKPiAgICoKPiArICogQHJlZ3M6CQkJYSBjb250aWd1b3VzIGNodW5rIG9m IG1lbW9yeSBmb3IgRE1BIHJlZ2lzdGVyCj4gKyAqCQkJCXdyaXRlcy4gY29udGFpbnMgdGhlIHJl Z2lzdGVyIHZhbHVlcyB0byBiZQo+ICsgKgkJCQl3cml0dGVuIHRvIGNvbnRyb2xsZXIKPiArICoK PiArICogQHByb3BzOgkJCXByb3BlcnRpZXMgb2YgY3VycmVudCBOQU5EIGNvbnRyb2xsZXIsCj4g KyAqCQkJCWluaXRpYWxpemVkIHZpYSBEVCBtYXRjaCBkYXRhCj4gKyAqCj4gKyAqIEBjb250cm9s bGVyOgkJCWJhc2UgY29udHJvbGxlciBzdHJ1Y3R1cmUKPiArICogQGhvc3RfbGlzdDoJCQlsaXN0 IGNvbnRhaW5pbmcgYWxsIHRoZSBjaGlwcyBhdHRhY2hlZCB0byB0aGUKPiArICoJCQkJY29udHJv bGxlcgo+ICsgKgo+ICAgKiBAY2hhbjoJCQlkbWEgY2hhbm5lbAo+ICAgKiBAY21kX2NyY2k6CQkJ QURNIERNQSBDUkNJIGZvciBjb21tYW5kIGZsb3cgY29udHJvbAo+ICAgKiBAZGF0YV9jcmNpOgkJ CUFETSBETUEgQ1JDSSBmb3IgZGF0YSBmbG93IGNvbnRyb2wKPiArICoKPiAgICogQGRlc2NfbGlz dDoJCQlETUEgZGVzY3JpcHRvciBsaXN0IChsaXN0IG9mIGRlc2NfaW5mb3MpCj4gICAqCj4gICAq IEBkYXRhX2J1ZmZlcjoJCW91ciBsb2NhbCBETUEgYnVmZmVyIGZvciBwYWdlIHJlYWQvd3JpdGVz LAo+ICAgKgkJCQl1c2VkIHdoZW4gd2UgY2FuJ3QgdXNlIHRoZSBidWZmZXIgcHJvdmlkZWQKPiAg ICoJCQkJYnkgdXBwZXIgbGF5ZXJzIGRpcmVjdGx5Cj4gLSAqIEBidWZfc2l6ZS9jb3VudC9zdGFy dDoJbWFya2VycyBmb3IgY2hpcC0+bGVnYWN5LnJlYWRfYnVmL3dyaXRlX2J1Zgo+IC0gKgkJCQlm dW5jdGlvbnMKPiAgICogQHJlZ19yZWFkX2J1ZjoJCWxvY2FsIGJ1ZmZlciBmb3IgcmVhZGluZyBi YWNrIHJlZ2lzdGVycyB2aWEgRE1BCj4gKyAqCj4gKyAqIEBiYXNlX3BoeXM6CQkJcGh5c2ljYWwg YmFzZSBhZGRyZXNzIG9mIGNvbnRyb2xsZXIgcmVnaXN0ZXJzCj4gKyAqIEBiYXNlX2RtYToJCQlk bWEgYmFzZSBhZGRyZXNzIG9mIGNvbnRyb2xsZXIgcmVnaXN0ZXJzCj4gICAqIEByZWdfcmVhZF9k bWE6CQljb250YWlucyBkbWEgYWRkcmVzcyBmb3IgcmVnaXN0ZXIgcmVhZCBidWZmZXIKPiAtICog QHJlZ19yZWFkX3BvczoJCW1hcmtlciBmb3IgZGF0YSByZWFkIGluIHJlZ19yZWFkX2J1Zgo+ICAg Kgo+IC0gKiBAcmVnczoJCQlhIGNvbnRpZ3VvdXMgY2h1bmsgb2YgbWVtb3J5IGZvciBETUEgcmVn aXN0ZXIKPiAtICoJCQkJd3JpdGVzLiBjb250YWlucyB0aGUgcmVnaXN0ZXIgdmFsdWVzIHRvIGJl Cj4gLSAqCQkJCXdyaXR0ZW4gdG8gY29udHJvbGxlcgo+IC0gKiBAY21kMS92bGQ6CQkJc29tZSBm aXhlZCBjb250cm9sbGVyIHJlZ2lzdGVyIHZhbHVlcwo+IC0gKiBAcHJvcHM6CQkJcHJvcGVydGll cyBvZiBjdXJyZW50IE5BTkQgY29udHJvbGxlciwKPiAtICoJCQkJaW5pdGlhbGl6ZWQgdmlhIERU IG1hdGNoIGRhdGEKPiArICogQGJ1Zl9zaXplL2NvdW50L3N0YXJ0OgltYXJrZXJzIGZvciBjaGlw LT5sZWdhY3kucmVhZF9idWYvd3JpdGVfYnVmCj4gKyAqCQkJCWZ1bmN0aW9ucwo+ICAgKiBAbWF4 X2N3cGVycGFnZToJCW1heGltdW0gUVBJQyBjb2Rld29yZHMgcmVxdWlyZWQuIGNhbGN1bGF0ZWQK PiAgICoJCQkJZnJvbSBhbGwgY29ubmVjdGVkIE5BTkQgZGV2aWNlcyBwYWdlc2l6ZQo+ICsgKgo+ ICsgKiBAcmVnX3JlYWRfcG9zOgkJbWFya2VyIGZvciBkYXRhIHJlYWQgaW4gcmVnX3JlYWRfYnVm Cj4gKyAqCj4gKyAqIEBjbWQxL3ZsZDoJCQlzb21lIGZpeGVkIGNvbnRyb2xsZXIgcmVnaXN0ZXIg dmFsdWVzCj4gICAqLwo+ICBzdHJ1Y3QgcWNvbV9uYW5kX2NvbnRyb2xsZXIgewo+IC0Jc3RydWN0 IG5hbmRfY29udHJvbGxlciBjb250cm9sbGVyOwo+IC0Jc3RydWN0IGxpc3RfaGVhZCBob3N0X2xp c3Q7Cj4gLQo+ICAJc3RydWN0IGRldmljZSAqZGV2Owo+ICAKPiAgCXZvaWQgX19pb21lbSAqYmFz ZTsKPiAtCXBoeXNfYWRkcl90IGJhc2VfcGh5czsKPiAtCWRtYV9hZGRyX3QgYmFzZV9kbWE7Cj4g IAo+ICAJc3RydWN0IGNsayAqY29yZV9jbGs7Cj4gIAlzdHJ1Y3QgY2xrICphb25fY2xrOwo+ICAK PiArCXN0cnVjdCBuYW5kY19yZWdzICpyZWdzOwo+ICsJc3RydWN0IGJhbV90cmFuc2FjdGlvbiAq YmFtX3R4bjsKPiArCj4gKwljb25zdCBzdHJ1Y3QgcWNvbV9uYW5kY19wcm9wcyAqcHJvcHM7Cj4g Kwo+ICsJc3RydWN0IG5hbmRfY29udHJvbGxlciBjb250cm9sbGVyOwo+ICsJc3RydWN0IGxpc3Rf aGVhZCBob3N0X2xpc3Q7Cj4gKwo+ICAJdW5pb24gewo+ICAJCS8qIHdpbGwgYmUgdXNlZCBvbmx5 IGJ5IFFQSUMgZm9yIEJBTSBETUEgKi8KPiAgCQlzdHJ1Y3Qgewo+IEBAIC00MDAsMjIgKzQxMywy MiBAQCBzdHJ1Y3QgcWNvbV9uYW5kX2NvbnRyb2xsZXIgewo+ICAJfTsKPiAgCj4gIAlzdHJ1Y3Qg bGlzdF9oZWFkIGRlc2NfbGlzdDsKPiAtCXN0cnVjdCBiYW1fdHJhbnNhY3Rpb24gKmJhbV90eG47 Cj4gIAo+ICAJdTgJCSpkYXRhX2J1ZmZlcjsKPiArCV9fbGUzMgkJKnJlZ19yZWFkX2J1ZjsKPiAr Cj4gKwlwaHlzX2FkZHJfdCBiYXNlX3BoeXM7Cj4gKwlkbWFfYWRkcl90IGJhc2VfZG1hOwo+ICsJ ZG1hX2FkZHJfdCByZWdfcmVhZF9kbWE7Cj4gKwo+ICAJaW50CQlidWZfc2l6ZTsKPiAgCWludAkJ YnVmX2NvdW50Owo+ICAJaW50CQlidWZfc3RhcnQ7Cj4gIAl1bnNpZ25lZCBpbnQJbWF4X2N3cGVy cGFnZTsKPiAgCj4gLQlfX2xlMzIgKnJlZ19yZWFkX2J1ZjsKPiAtCWRtYV9hZGRyX3QgcmVnX3Jl YWRfZG1hOwo+ICAJaW50IHJlZ19yZWFkX3BvczsKPiAgCj4gLQlzdHJ1Y3QgbmFuZGNfcmVncyAq cmVnczsKPiAtCj4gIAl1MzIgY21kMSwgdmxkOwo+IC0JY29uc3Qgc3RydWN0IHFjb21fbmFuZGNf cHJvcHMgKnByb3BzOwo+ICB9Owo+ICAKPiAgLyoKPiBAQCAtNDMxLDE5ICs0NDQsMjEgQEAgc3Ry dWN0IHFjb21fbmFuZF9jb250cm9sbGVyIHsKPiAgICoJCQkJYW5kIHJlc2VydmVkIGJ5dGVzCj4g ICAqIEBjd19kYXRhOgkJCXRoZSBudW1iZXIgb2YgYnl0ZXMgd2l0aGluIGEgY29kZXdvcmQgcHJv dGVjdGVkCj4gICAqCQkJCWJ5IEVDQwo+IC0gKiBAdXNlX2VjYzoJCQlyZXF1ZXN0IHRoZSBjb250 cm9sbGVyIHRvIHVzZSBFQ0MgZm9yIHRoZQo+IC0gKgkJCQl1cGNvbWluZyByZWFkL3dyaXRlCj4g LSAqIEBiY2hfZW5hYmxlZDoJCWZsYWcgdG8gdGVsbCB3aGV0aGVyIEJDSCBFQ0MgbW9kZSBpcyB1 c2VkCj4gICAqIEBlY2NfYnl0ZXNfaHc6CQlFQ0MgYnl0ZXMgdXNlZCBieSBjb250cm9sbGVyIGhh cmR3YXJlIGZvciB0aGlzCj4gICAqCQkJCWNoaXAKPiAtICogQHN0YXR1czoJCQl2YWx1ZSB0byBi ZSByZXR1cm5lZCBpZiBOQU5EX0NNRF9TVEFUVVMgY29tbWFuZAo+IC0gKgkJCQlpcyBleGVjdXRl ZAo+ICsgKgo+ICAgKiBAbGFzdF9jb21tYW5kOgkJa2VlcHMgdHJhY2sgb2YgbGFzdCBjb21tYW5k IG9uIHRoaXMgY2hpcC4gdXNlZAo+ICAgKgkJCQlmb3IgcmVhZGluZyBjb3JyZWN0IHN0YXR1cwo+ ICAgKgo+ICAgKiBAY2ZnMCwgY2ZnMSwgY2ZnMF9yYXcuLjoJTkFORGMgcmVnaXN0ZXIgY29uZmln dXJhdGlvbnMgbmVlZGVkIGZvcgo+ICAgKgkJCQllY2Mvbm9uLWVjYyBtb2RlIGZvciB0aGUgY3Vy cmVudCBuYW5kIGZsYXNoCj4gICAqCQkJCWRldmljZQo+ICsgKgo+ICsgKiBAc3RhdHVzOgkJCXZh bHVlIHRvIGJlIHJldHVybmVkIGlmIE5BTkRfQ01EX1NUQVRVUyBjb21tYW5kCj4gKyAqCQkJCWlz IGV4ZWN1dGVkCj4gKyAqIEB1c2VfZWNjOgkJCXJlcXVlc3QgdGhlIGNvbnRyb2xsZXIgdG8gdXNl IEVDQyBmb3IgdGhlCj4gKyAqCQkJCXVwY29taW5nIHJlYWQvd3JpdGUKPiArICogQGJjaF9lbmFi bGVkOgkJZmxhZyB0byB0ZWxsIHdoZXRoZXIgQkNIIEVDQyBtb2RlIGlzIHVzZWQKPiAgICovCj4g IHN0cnVjdCBxY29tX25hbmRfaG9zdCB7Cj4gIAlzdHJ1Y3QgbmFuZF9jaGlwIGNoaXA7Cj4gQEAg LTQ1MiwxMiArNDY3LDEwIEBAIHN0cnVjdCBxY29tX25hbmRfaG9zdCB7Cj4gIAlpbnQgY3M7Cj4g IAlpbnQgY3dfc2l6ZTsKPiAgCWludCBjd19kYXRhOwo+IC0JYm9vbCB1c2VfZWNjOwo+IC0JYm9v bCBiY2hfZW5hYmxlZDsKPiAgCWludCBlY2NfYnl0ZXNfaHc7Cj4gIAlpbnQgc3BhcmVfYnl0ZXM7 Cj4gIAlpbnQgYmJtX3NpemU7Cj4gLQl1OCBzdGF0dXM7Cj4gKwo+ICAJaW50IGxhc3RfY29tbWFu ZDsKPiAgCj4gIAl1MzIgY2ZnMCwgY2ZnMTsKPiBAQCAtNDY2LDIzICs0NzksMjcgQEAgc3RydWN0 IHFjb21fbmFuZF9ob3N0IHsKPiAgCXUzMiBlY2NfYmNoX2NmZzsKPiAgCXUzMiBjbHJmbGFzaHN0 YXR1czsKPiAgCXUzMiBjbHJyZWFkc3RhdHVzOwo+ICsKPiArCXU4IHN0YXR1czsKPiArCWJvb2wg dXNlX2VjYzsKPiArCWJvb2wgYmNoX2VuYWJsZWQ7Cj4gIH07Cj4gIAo+ICAvKgo+ICAgKiBUaGlz IGRhdGEgdHlwZSBjb3JyZXNwb25kcyB0byB0aGUgTkFORCBjb250cm9sbGVyIHByb3BlcnRpZXMg d2hpY2ggdmFyaWVzCj4gICAqIGFtb25nIGRpZmZlcmVudCBOQU5EIGNvbnRyb2xsZXJzLgo+ICAg KiBAZWNjX21vZGVzIC0gZWNjIG1vZGUgZm9yIE5BTkQKPiArICogQGRldl9jbWRfcmVnX3N0YXJ0 IC0gTkFORF9ERVZfQ01EXyogcmVnaXN0ZXJzIHN0YXJ0aW5nIG9mZnNldAo+ICAgKiBAaXNfYmFt IC0gd2hldGhlciBOQU5EIGNvbnRyb2xsZXIgaXMgdXNpbmcgQkFNCj4gICAqIEBpc19xcGljIC0g d2hldGhlciBOQU5EIENUUkwgaXMgcGFydCBvZiBxcGljIElQCj4gICAqIEBxcGljX3YyIC0gZmxh ZyB0byBpbmRpY2F0ZSBRUElDIElQIHZlcnNpb24gMgo+IC0gKiBAZGV2X2NtZF9yZWdfc3RhcnQg LSBOQU5EX0RFVl9DTURfKiByZWdpc3RlcnMgc3RhcnRpbmcgb2Zmc2V0Cj4gICAqLwo+ICBzdHJ1 Y3QgcWNvbV9uYW5kY19wcm9wcyB7Cj4gIAl1MzIgZWNjX21vZGVzOwo+ICsJdTMyIGRldl9jbWRf cmVnX3N0YXJ0Owo+ICAJYm9vbCBpc19iYW07Cj4gIAlib29sIGlzX3FwaWM7Cj4gIAlib29sIHFw aWNfdjI7Cj4gLQl1MzIgZGV2X2NtZF9yZWdfc3RhcnQ7Cj4gIH07Cj4gIAo+ICAvKiBGcmVlcyB0 aGUgQkFNIHRyYW5zYWN0aW9uIG1lbW9yeSAqLwo+IC0tIAo+IDIuMzYuMQo+IAoKLS0gCuCuruCu o+Cuv+CuteCuo+CvjeCuo+CuqeCvjSDgrprgrqTgrr7grprgrr/grrXgrq7gr40KCl9fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpMaW51eCBNVEQg ZGlzY3Vzc2lvbiBtYWlsaW5nIGxpc3QKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1h bi9saXN0aW5mby9saW51eC1tdGQvCg==