From: Gregory Etelson <getelson@nvidia.com>
To: <dev@dpdk.org>
Cc: <getelson@nvidia.com>, <matan@nvidia.com>, <rasland@nvidia.com>,
<stable@dpdk.org>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Subject: [PATCH v2] doc: fix mlx5 flow integrity hardware support
Date: Thu, 16 Jun 2022 11:43:14 +0300 [thread overview]
Message-ID: <20220616084314.6464-1-getelson@nvidia.com> (raw)
In-Reply-To: <20220616075215.4622-1-getelson@nvidia.com>
Current MLX5 PMD documentation stays that entire `ConnentX-6` family
supports flow integrity feature.
Flow integrity offload is not supported on vanilla `ConnectX-6`.
It is available on `ConnectX-6 DX`, `ConnectX-6 LX` and
`BlueField-2`.
Cc: stable@dpdk.org
Fixes: 79f8952783d0 ("net/mlx5: support integrity flow item")
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
v2: Update Mellanox hardware types that support integrity bits.
---
doc/guides/nics/mlx5.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index f41703277e..978886ad88 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -458,7 +458,7 @@ Limitations
- Integrity:
- - Integrity offload is enabled for **ConnectX-6** family.
+ - Integrity offload is enabled starting from **ConnectX-6 DX**.
- Verification bits provided by the hardware are ``l3_ok``, ``ipv4_csum_ok``, ``l4_ok``, ``l4_csum_ok``.
- ``level`` value 0 references outer headers.
- Multiple integrity items not supported in a single flow rule.
--
2.34.1
next prev parent reply other threads:[~2022-06-16 8:43 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-16 7:52 [PATCH] doc: fix mlx5 flow integrity hardware support Gregory Etelson
2022-06-16 8:43 ` Gregory Etelson [this message]
2022-06-20 8:03 ` [PATCH v2] " Raslan Darawsheh
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