From: Christoph Hellwig <hch@lst.de>
To: "Heiko Stübner" <heiko@sntech.de>
Cc: Christoph Hellwig <hch@lst.de>,
palmer@dabbelt.com, paul.walmsley@sifive.com,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
wefu@redhat.com, guoren@kernel.org, cmuellner@linux.com,
philipp.tomsich@vrull.eu, samuel@sholland.org,
atishp@atishpatra.org, anup@brainfault.org, mick@ics.forth.gr,
robh+dt@kernel.org, krzk+dt@kernel.org,
devicetree@vger.kernel.org, drew@beagleboard.org,
Atish Patra <atish.patra@wdc.com>
Subject: Re: [PATCH 2/3] riscv: Implement Zicbom-based cache management operations
Date: Thu, 16 Jun 2022 14:11:57 +0200 [thread overview]
Message-ID: <20220616121157.GA11657@lst.de> (raw)
In-Reply-To: <2041345.KlZ2vcFHjT@diego>
On Thu, Jun 16, 2022 at 02:09:47PM +0200, Heiko Stübner wrote:
> My guess was that new platforms implementing cache-management will want
> to be non-coherent by default?
No. Cache incoherent DMA is absolutely horrible and almost impossible
to get right for the corner cases. It is a cost cutting measure seen on
cheap SOCs and mostly avoided for more enterprise grade products.
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WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: "Heiko Stübner" <heiko@sntech.de>
Cc: Christoph Hellwig <hch@lst.de>,
palmer@dabbelt.com, paul.walmsley@sifive.com,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
wefu@redhat.com, guoren@kernel.org, cmuellner@linux.com,
philipp.tomsich@vrull.eu, samuel@sholland.org,
atishp@atishpatra.org, anup@brainfault.org, mick@ics.forth.gr,
robh+dt@kernel.org, krzk+dt@kernel.org,
devicetree@vger.kernel.org, drew@beagleboard.org,
Atish Patra <atish.patra@wdc.com>
Subject: Re: [PATCH 2/3] riscv: Implement Zicbom-based cache management operations
Date: Thu, 16 Jun 2022 14:11:57 +0200 [thread overview]
Message-ID: <20220616121157.GA11657@lst.de> (raw)
In-Reply-To: <2041345.KlZ2vcFHjT@diego>
On Thu, Jun 16, 2022 at 02:09:47PM +0200, Heiko Stübner wrote:
> My guess was that new platforms implementing cache-management will want
> to be non-coherent by default?
No. Cache incoherent DMA is absolutely horrible and almost impossible
to get right for the corner cases. It is a cost cutting measure seen on
cheap SOCs and mostly avoided for more enterprise grade products.
next prev parent reply other threads:[~2022-06-16 12:12 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-10 0:43 [PATCH v3 0/3] riscv: implement Zicbom-based CMO instructions + the t-head variant Heiko Stuebner
2022-06-10 0:43 ` Heiko Stuebner
2022-06-10 0:43 ` [PATCH 1/3] dt-bindings: riscv: document cbom-block-size Heiko Stuebner
2022-06-10 0:43 ` Heiko Stuebner
2022-06-17 20:37 ` Rob Herring
2022-06-17 20:37 ` Rob Herring
2022-06-10 0:43 ` [PATCH 2/3] riscv: Implement Zicbom-based cache management operations Heiko Stuebner
2022-06-10 0:43 ` Heiko Stuebner
2022-06-10 3:22 ` Randy Dunlap
2022-06-10 3:22 ` Randy Dunlap
2022-06-10 5:56 ` Christoph Hellwig
2022-06-10 5:56 ` Christoph Hellwig
2022-06-15 16:56 ` Heiko Stübner
2022-06-15 16:56 ` Heiko Stübner
2022-06-15 17:49 ` Christoph Hellwig
2022-06-15 17:49 ` Christoph Hellwig
2022-06-16 9:46 ` Heiko Stübner
2022-06-16 9:46 ` Heiko Stübner
2022-06-16 11:53 ` Christoph Hellwig
2022-06-16 11:53 ` Christoph Hellwig
2022-06-16 12:09 ` Heiko Stübner
2022-06-16 12:09 ` Heiko Stübner
2022-06-16 12:11 ` Christoph Hellwig [this message]
2022-06-16 12:11 ` Christoph Hellwig
2022-06-17 8:30 ` Heiko Stübner
2022-06-17 8:30 ` Heiko Stübner
2022-06-12 19:15 ` Samuel Holland
2022-06-12 19:15 ` Samuel Holland
2022-06-13 5:50 ` Christoph Hellwig
2022-06-13 5:50 ` Christoph Hellwig
2022-06-10 0:43 ` [PATCH 3/3] riscv: implement cache-management errata for T-Head SoCs Heiko Stuebner
2022-06-10 0:43 ` Heiko Stuebner
2022-06-10 1:04 ` Guo Ren
2022-06-10 1:04 ` Guo Ren
2022-06-12 19:18 ` Samuel Holland
2022-06-12 19:18 ` Samuel Holland
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