From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5CC8C433EF for ; Thu, 16 Jun 2022 20:30:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378368AbiFPUaZ (ORCPT ); Thu, 16 Jun 2022 16:30:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231592AbiFPUaY (ORCPT ); Thu, 16 Jun 2022 16:30:24 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 672195C775; Thu, 16 Jun 2022 13:30:23 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 00691B82604; Thu, 16 Jun 2022 20:30:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E4A56C34114; Thu, 16 Jun 2022 20:30:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655411420; bh=gqpc49ti+Zgnw3+agp61Jjcjcq6cNofAamXaJBtkMDc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Na0lYLZBrdmynN+OtW4+Wut8svKDLYeLf/XqpN/8+UO5U7pkTHlOQFdW9snOchhGX uDpnFNsxb6MQ0sH9Cj5E6HSg5oami+V/uKCbKKF05upxgbHaeHxZCp8xhcTA6OgjR3 x7f0TjcVrqRAqdD6fSbbRudOmuSzKsogDUgMvDjuIdIEE2Qy64poELfWmDvtEc9JM8 pspx415OaLLub0TqMbDrXFaF9jt4a1U3X9emMkEZ2IKlkqLDApFQXy79LR/Bk2VD47 uF4zXLPXO0ziX7dH38LTOR23lRZgc/FPlo3hKnWToZ9ieH/kyWc3HY6IsuOSYRuGlh g9xuiFekEsGQw== Date: Fri, 17 Jun 2022 02:00:19 +0530 From: Manivannan Sadhasivam To: Christian Marangi Cc: Andy Gross , Bjorn Andersson , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v8 2/3] mtd: nand: raw: qcom_nandc: add support for unprotected spare data pages Message-ID: <20220616203019.GD2889@thinkpad> References: <20220616001835.24393-1-ansuelsmth@gmail.com> <20220616001835.24393-3-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220616001835.24393-3-ansuelsmth@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Thu, Jun 16, 2022 at 02:18:34AM +0200, Christian Marangi wrote: > IPQ8064 nand have special pages where a different layout scheme is used. > These special page are used by boot partition and on reading them > lots of warning are reported about wrong ECC data and if written to > results in broken data and not bootable device. > > The layout scheme used by these special page consist in using 512 bytes > as the codeword size (even for the last codeword) while writing to CFG0 > register. This forces the NAND controller to unprotect the 4 bytes of > spare data. > > Since the kernel is unaware of this different layout for these special > page, it does try to protect the spare data too during read/write and > warn about CRC errors. > > Add support for this by permitting the user to declare these special > pages in dts by declaring offset and size of the partition. The driver > internally will convert these value to nand pages. > > On user read/write the page is checked and if it's a boot page the > correct layout is used. > > Signed-off-by: Christian Marangi Reviewed-by: Manivannan Sadhasivam Thanks, Mani > --- > drivers/mtd/nand/raw/qcom_nandc.c | 199 +++++++++++++++++++++++++++++- > 1 file changed, 194 insertions(+), 5 deletions(-) > > diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c > index f2990d721733..ce1cb048bafc 100644 > --- a/drivers/mtd/nand/raw/qcom_nandc.c > +++ b/drivers/mtd/nand/raw/qcom_nandc.c > @@ -80,8 +80,10 @@ > #define DISABLE_STATUS_AFTER_WRITE 4 > #define CW_PER_PAGE 6 > #define UD_SIZE_BYTES 9 > +#define UD_SIZE_BYTES_MASK GENMASK(18, 9) > #define ECC_PARITY_SIZE_BYTES_RS 19 > #define SPARE_SIZE_BYTES 23 > +#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23) > #define NUM_ADDR_CYCLES 27 > #define STATUS_BFR_READ 30 > #define SET_RD_MODE_AFTER_STATUS 31 > @@ -102,6 +104,7 @@ > #define ECC_MODE 4 > #define ECC_PARITY_SIZE_BYTES_BCH 8 > #define ECC_NUM_DATA_BYTES 16 > +#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16) > #define ECC_FORCE_CLK_OPEN 30 > > /* NAND_DEV_CMD1 bits */ > @@ -431,13 +434,32 @@ struct qcom_nand_controller { > u32 cmd1, vld; > }; > > +/* > + * NAND special boot partitions > + * > + * @page_offset: offset of the partition where spare data is not protected > + * by ECC (value in pages) > + * @page_offset: size of the partition where spare data is not protected > + * by ECC (value in pages) > + */ > +struct qcom_nand_boot_partition { > + u32 page_offset; > + u32 page_size; > +}; > + > /* > * NAND chip structure > * > + * @boot_partitions: array of boot partitions where offset and size of the > + * boot partitions are stored > + * > * @chip: base NAND chip structure > * @node: list node to add itself to host_list in > * qcom_nand_controller > * > + * @nr_boot_partitions: count of the boot partitions where spare data is not > + * protected by ECC > + * > * @cs: chip select value for this chip > * @cw_size: the number of bytes in a single step/codeword > * of a page, consisting of all data, ecc, spare > @@ -456,14 +478,20 @@ struct qcom_nand_controller { > * > * @status: value to be returned if NAND_CMD_STATUS command > * is executed > + * @codeword_fixup: keep track of the current layout used by > + * the driver for read/write operation. > * @use_ecc: request the controller to use ECC for the > * upcoming read/write > * @bch_enabled: flag to tell whether BCH ECC mode is used > */ > struct qcom_nand_host { > + struct qcom_nand_boot_partition *boot_partitions; > + > struct nand_chip chip; > struct list_head node; > > + int nr_boot_partitions; > + > int cs; > int cw_size; > int cw_data; > @@ -481,6 +509,7 @@ struct qcom_nand_host { > u32 clrreadstatus; > > u8 status; > + bool codeword_fixup; > bool use_ecc; > bool bch_enabled; > }; > @@ -493,6 +522,7 @@ struct qcom_nand_host { > * @is_bam - whether NAND controller is using BAM > * @is_qpic - whether NAND CTRL is part of qpic IP > * @qpic_v2 - flag to indicate QPIC IP version 2 > + * @use_codeword_fixup - whether NAND has different layout for boot partitions > */ > struct qcom_nandc_props { > u32 ecc_modes; > @@ -500,6 +530,7 @@ struct qcom_nandc_props { > bool is_bam; > bool is_qpic; > bool qpic_v2; > + bool use_codeword_fixup; > }; > > /* Frees the BAM transaction memory */ > @@ -1718,7 +1749,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip, > data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); > oob_size1 = host->bbm_size; > > - if (qcom_nandc_is_last_cw(ecc, cw)) { > + if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { > data_size2 = ecc->size - data_size1 - > ((ecc->steps - 1) * 4); > oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw + > @@ -1799,7 +1830,7 @@ check_for_erased_page(struct qcom_nand_host *host, u8 *data_buf, > } > > for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) { > - if (qcom_nandc_is_last_cw(ecc, cw)) { > + if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) { > data_size = ecc->size - ((ecc->steps - 1) * 4); > oob_size = (ecc->steps * 4) + host->ecc_bytes_hw; > } else { > @@ -1957,7 +1988,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf, > for (i = 0; i < ecc->steps; i++) { > int data_size, oob_size; > > - if (qcom_nandc_is_last_cw(ecc, i)) { > + if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { > data_size = ecc->size - ((ecc->steps - 1) << 2); > oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + > host->spare_bytes; > @@ -2054,6 +2085,69 @@ static int copy_last_cw(struct qcom_nand_host *host, int page) > return ret; > } > > +static bool qcom_nandc_is_boot_partition(struct qcom_nand_host *host, int page) > +{ > + struct qcom_nand_boot_partition *boot_partition; > + u32 start, end; > + int i; > + > + /* > + * Since the frequent access will be to the non-boot partitions like rootfs, > + * optimize the page check by: > + * > + * 1. Checking if the page lies after the last boot partition. > + * 2. Checking from the boot partition end. > + */ > + > + /* First check the last boot partition */ > + boot_partition = &host->boot_partitions[host->nr_boot_partitions - 1]; > + start = boot_partition->page_offset; > + end = start + boot_partition->page_size; > + > + /* Page is after the last boot partition end. This is NOT a boot partition */ > + if (page > end) > + return false; > + > + /* Actually check if it's a boot partition */ > + if (page < end && page >= start) > + return true; > + > + /* Check the other boot partitions starting from the second-last partition */ > + for (i = host->nr_boot_partitions - 2; i >= 0; i--) { > + boot_partition = &host->boot_partitions[i]; > + start = boot_partition->page_offset; > + end = start + boot_partition->page_size; > + > + if (page < end && page >= start) > + return true; > + } > + > + return false; > +} > + > +static void qcom_nandc_codeword_fixup(struct qcom_nand_host *host, int page) > +{ > + bool codeword_fixup = qcom_nandc_is_boot_partition(host, page); > + > + /* Skip conf write if we are already in the correct mode */ > + if (codeword_fixup == host->codeword_fixup) > + return; > + > + host->codeword_fixup = codeword_fixup; > + > + host->cw_data = codeword_fixup ? 512 : 516; > + host->spare_bytes = host->cw_size - host->ecc_bytes_hw - > + host->bbm_size - host->cw_data; > + > + host->cfg0 &= ~(SPARE_SIZE_BYTES_MASK | UD_SIZE_BYTES_MASK); > + host->cfg0 |= host->spare_bytes << SPARE_SIZE_BYTES | > + host->cw_data << UD_SIZE_BYTES; > + > + host->ecc_bch_cfg &= ~ECC_NUM_DATA_BYTES_MASK; > + host->ecc_bch_cfg |= host->cw_data << ECC_NUM_DATA_BYTES; > + host->ecc_buf_cfg = (host->cw_data - 1) << NUM_STEPS; > +} > + > /* implements ecc->read_page() */ > static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf, > int oob_required, int page) > @@ -2062,6 +2156,9 @@ static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf, > struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); > u8 *data_buf, *oob_buf = NULL; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > nand_read_page_op(chip, page, 0, NULL, 0); > data_buf = buf; > oob_buf = oob_required ? chip->oob_poi : NULL; > @@ -2081,6 +2178,9 @@ static int qcom_nandc_read_page_raw(struct nand_chip *chip, uint8_t *buf, > int cw, ret; > u8 *data_buf = buf, *oob_buf = chip->oob_poi; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > for (cw = 0; cw < ecc->steps; cw++) { > ret = qcom_nandc_read_cw_raw(mtd, chip, data_buf, oob_buf, > page, cw); > @@ -2101,6 +2201,9 @@ static int qcom_nandc_read_oob(struct nand_chip *chip, int page) > struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); > struct nand_ecc_ctrl *ecc = &chip->ecc; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > clear_read_regs(nandc); > clear_bam_transaction(nandc); > > @@ -2121,6 +2224,9 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const uint8_t *buf, > u8 *data_buf, *oob_buf; > int i, ret; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > nand_prog_page_begin_op(chip, page, 0, NULL, 0); > > clear_read_regs(nandc); > @@ -2136,7 +2242,7 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const uint8_t *buf, > for (i = 0; i < ecc->steps; i++) { > int data_size, oob_size; > > - if (qcom_nandc_is_last_cw(ecc, i)) { > + if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { > data_size = ecc->size - ((ecc->steps - 1) << 2); > oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + > host->spare_bytes; > @@ -2193,6 +2299,9 @@ static int qcom_nandc_write_page_raw(struct nand_chip *chip, > u8 *data_buf, *oob_buf; > int i, ret; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > nand_prog_page_begin_op(chip, page, 0, NULL, 0); > clear_read_regs(nandc); > clear_bam_transaction(nandc); > @@ -2211,7 +2320,7 @@ static int qcom_nandc_write_page_raw(struct nand_chip *chip, > data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); > oob_size1 = host->bbm_size; > > - if (qcom_nandc_is_last_cw(ecc, i)) { > + if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) { > data_size2 = ecc->size - data_size1 - > ((ecc->steps - 1) << 2); > oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + > @@ -2271,6 +2380,9 @@ static int qcom_nandc_write_oob(struct nand_chip *chip, int page) > int data_size, oob_size; > int ret; > > + if (host->nr_boot_partitions) > + qcom_nandc_codeword_fixup(host, page); > + > host->use_ecc = true; > clear_bam_transaction(nandc); > > @@ -2919,6 +3031,74 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc) > > static const char * const probes[] = { "cmdlinepart", "ofpart", "qcomsmem", NULL }; > > +static int qcom_nand_host_parse_boot_partitions(struct qcom_nand_controller *nandc, > + struct qcom_nand_host *host, > + struct device_node *dn) > +{ > + struct nand_chip *chip = &host->chip; > + struct mtd_info *mtd = nand_to_mtd(chip); > + struct qcom_nand_boot_partition *boot_partition; > + struct device *dev = nandc->dev; > + int partitions_count, i, j, ret; > + > + if (!of_find_property(dn, "qcom,boot-partitions", NULL)) > + return 0; > + > + partitions_count = of_property_count_u32_elems(dn, "qcom,boot-partitions"); > + if (partitions_count <= 0) { > + dev_err(dev, "Error parsing boot partition\n"); > + return partitions_count ? partitions_count : -EINVAL; > + } > + > + host->nr_boot_partitions = partitions_count / 2; > + host->boot_partitions = devm_kcalloc(dev, host->nr_boot_partitions, > + sizeof(*host->boot_partitions), GFP_KERNEL); > + if (!host->boot_partitions) { > + host->nr_boot_partitions = 0; > + return -ENOMEM; > + } > + > + for (i = 0, j = 0; i < host->nr_boot_partitions; i++, j += 2) { > + boot_partition = &host->boot_partitions[i]; > + > + ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j, > + &boot_partition->page_offset); > + if (ret) { > + dev_err(dev, "Error parsing boot partition offset at index %d\n", i); > + host->nr_boot_partitions = 0; > + return ret; > + } > + > + if (boot_partition->page_offset % mtd->writesize) { > + dev_err(dev, "Boot partition offset not multiple of writesize at index %i\n", > + i); > + host->nr_boot_partitions = 0; > + return -EINVAL; > + } > + /* Convert offset to nand pages */ > + boot_partition->page_offset /= mtd->writesize; > + > + ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j + 1, > + &boot_partition->page_size); > + if (ret) { > + dev_err(dev, "Error parsing boot partition size at index %d\n", i); > + host->nr_boot_partitions = 0; > + return ret; > + } > + > + if (boot_partition->page_size % mtd->writesize) { > + dev_err(dev, "Boot partition size not multiple of writesize at index %i\n", > + i); > + host->nr_boot_partitions = 0; > + return -EINVAL; > + } > + /* Convert size to nand pages */ > + boot_partition->page_size /= mtd->writesize; > + } > + > + return 0; > +} > + > static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, > struct qcom_nand_host *host, > struct device_node *dn) > @@ -2987,6 +3167,14 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, > if (ret) > nand_cleanup(chip); > > + if (nandc->props->use_codeword_fixup) { > + ret = qcom_nand_host_parse_boot_partitions(nandc, host, dn); > + if (ret) { > + nand_cleanup(chip); > + return ret; > + } > + } > + > return ret; > } > > @@ -3152,6 +3340,7 @@ static int qcom_nandc_remove(struct platform_device *pdev) > static const struct qcom_nandc_props ipq806x_nandc_props = { > .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT), > .is_bam = false, > + .use_codeword_fixup = true, > .dev_cmd_reg_start = 0x0, > }; > > -- > 2.36.1 > -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A27BDC433EF for ; Thu, 16 Jun 2022 20:30:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YwTiyr4nTIhLhLdPg+yOm9+iCi4L+s1HC1FOLwrhlEk=; b=dUAD+0PEQvfGSy xMYtWtaNuvUqkBik3/Jgb+aMPGbQ4jMgsVcZ2wnESLpZ07BV5Uk/CSlpHdeD1wifAOKTpzZRBAEW6 7b2h85lszcv/A4Kdzhby3U3heCe8Wfwz6g3x/1D1tkQ0pQDfMHeNcjbh/uKHgTdR0qkrIK/FPCqP2 VZDqXAWZQkInas/kz3TP+zRE3kg8/ObNrdcqgh5yiuuvu2wJkVMLQA2W7McXJ9zwb/FTArTZ+6TLY cjCJ5WMVPMFQGCKJPLOLTQzF5pRgp1uQLS1clsK1w2ZNDXauerGS6aOIaV5hlUNoGfUOgs4Hyl57z akENxUonJh/gv+pmLGAQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o1w8I-0048cS-6J; Thu, 16 Jun 2022 20:30:26 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o1w8D-0048Zy-R2 for linux-mtd@lists.infradead.org; Thu, 16 Jun 2022 20:30:24 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 55A4F61DED; Thu, 16 Jun 2022 20:30:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E4A56C34114; Thu, 16 Jun 2022 20:30:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655411420; bh=gqpc49ti+Zgnw3+agp61Jjcjcq6cNofAamXaJBtkMDc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Na0lYLZBrdmynN+OtW4+Wut8svKDLYeLf/XqpN/8+UO5U7pkTHlOQFdW9snOchhGX uDpnFNsxb6MQ0sH9Cj5E6HSg5oami+V/uKCbKKF05upxgbHaeHxZCp8xhcTA6OgjR3 x7f0TjcVrqRAqdD6fSbbRudOmuSzKsogDUgMvDjuIdIEE2Qy64poELfWmDvtEc9JM8 pspx415OaLLub0TqMbDrXFaF9jt4a1U3X9emMkEZ2IKlkqLDApFQXy79LR/Bk2VD47 uF4zXLPXO0ziX7dH38LTOR23lRZgc/FPlo3hKnWToZ9ieH/kyWc3HY6IsuOSYRuGlh g9xuiFekEsGQw== Date: Fri, 17 Jun 2022 02:00:19 +0530 From: Manivannan Sadhasivam To: Christian Marangi Cc: Andy Gross , Bjorn Andersson , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v8 2/3] mtd: nand: raw: qcom_nandc: add support for unprotected spare data pages Message-ID: <20220616203019.GD2889@thinkpad> References: <20220616001835.24393-1-ansuelsmth@gmail.com> <20220616001835.24393-3-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220616001835.24393-3-ansuelsmth@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220616_133021_999151_86065434 X-CRM114-Status: GOOD ( 50.11 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org T24gVGh1LCBKdW4gMTYsIDIwMjIgYXQgMDI6MTg6MzRBTSArMDIwMCwgQ2hyaXN0aWFuIE1hcmFu Z2kgd3JvdGU6Cj4gSVBRODA2NCBuYW5kIGhhdmUgc3BlY2lhbCBwYWdlcyB3aGVyZSBhIGRpZmZl cmVudCBsYXlvdXQgc2NoZW1lIGlzIHVzZWQuCj4gVGhlc2Ugc3BlY2lhbCBwYWdlIGFyZSB1c2Vk IGJ5IGJvb3QgcGFydGl0aW9uIGFuZCBvbiByZWFkaW5nIHRoZW0KPiBsb3RzIG9mIHdhcm5pbmcg YXJlIHJlcG9ydGVkIGFib3V0IHdyb25nIEVDQyBkYXRhIGFuZCBpZiB3cml0dGVuIHRvCj4gcmVz dWx0cyBpbiBicm9rZW4gZGF0YSBhbmQgbm90IGJvb3RhYmxlIGRldmljZS4KPiAKPiBUaGUgbGF5 b3V0IHNjaGVtZSB1c2VkIGJ5IHRoZXNlIHNwZWNpYWwgcGFnZSBjb25zaXN0IGluIHVzaW5nIDUx MiBieXRlcwo+IGFzIHRoZSBjb2Rld29yZCBzaXplIChldmVuIGZvciB0aGUgbGFzdCBjb2Rld29y ZCkgd2hpbGUgd3JpdGluZyB0byBDRkcwCj4gcmVnaXN0ZXIuIFRoaXMgZm9yY2VzIHRoZSBOQU5E IGNvbnRyb2xsZXIgdG8gdW5wcm90ZWN0IHRoZSA0IGJ5dGVzIG9mCj4gc3BhcmUgZGF0YS4KPiAK PiBTaW5jZSB0aGUga2VybmVsIGlzIHVuYXdhcmUgb2YgdGhpcyBkaWZmZXJlbnQgbGF5b3V0IGZv ciB0aGVzZSBzcGVjaWFsCj4gcGFnZSwgaXQgZG9lcyB0cnkgdG8gcHJvdGVjdCB0aGUgc3BhcmUg ZGF0YSB0b28gZHVyaW5nIHJlYWQvd3JpdGUgYW5kCj4gd2FybiBhYm91dCBDUkMgZXJyb3JzLgo+ IAo+IEFkZCBzdXBwb3J0IGZvciB0aGlzIGJ5IHBlcm1pdHRpbmcgdGhlIHVzZXIgdG8gZGVjbGFy ZSB0aGVzZSBzcGVjaWFsCj4gcGFnZXMgaW4gZHRzIGJ5IGRlY2xhcmluZyBvZmZzZXQgYW5kIHNp emUgb2YgdGhlIHBhcnRpdGlvbi4gVGhlIGRyaXZlcgo+IGludGVybmFsbHkgd2lsbCBjb252ZXJ0 IHRoZXNlIHZhbHVlIHRvIG5hbmQgcGFnZXMuCj4gCj4gT24gdXNlciByZWFkL3dyaXRlIHRoZSBw YWdlIGlzIGNoZWNrZWQgYW5kIGlmIGl0J3MgYSBib290IHBhZ2UgdGhlCj4gY29ycmVjdCBsYXlv dXQgaXMgdXNlZC4KPiAKPiBTaWduZWQtb2ZmLWJ5OiBDaHJpc3RpYW4gTWFyYW5naSA8YW5zdWVs c210aEBnbWFpbC5jb20+CgpSZXZpZXdlZC1ieTogTWFuaXZhbm5hbiBTYWRoYXNpdmFtIDxtYW5p QGtlcm5lbC5vcmc+CgpUaGFua3MsCk1hbmkKCj4gLS0tCj4gIGRyaXZlcnMvbXRkL25hbmQvcmF3 L3Fjb21fbmFuZGMuYyB8IDE5OSArKysrKysrKysrKysrKysrKysrKysrKysrKysrKy0KPiAgMSBm aWxlIGNoYW5nZWQsIDE5NCBpbnNlcnRpb25zKCspLCA1IGRlbGV0aW9ucygtKQo+IAo+IGRpZmYg LS1naXQgYS9kcml2ZXJzL210ZC9uYW5kL3Jhdy9xY29tX25hbmRjLmMgYi9kcml2ZXJzL210ZC9u YW5kL3Jhdy9xY29tX25hbmRjLmMKPiBpbmRleCBmMjk5MGQ3MjE3MzMuLmNlMWNiMDQ4YmFmYyAx MDA2NDQKPiAtLS0gYS9kcml2ZXJzL210ZC9uYW5kL3Jhdy9xY29tX25hbmRjLmMKPiArKysgYi9k cml2ZXJzL210ZC9uYW5kL3Jhdy9xY29tX25hbmRjLmMKPiBAQCAtODAsOCArODAsMTAgQEAKPiAg I2RlZmluZQlESVNBQkxFX1NUQVRVU19BRlRFUl9XUklURQk0Cj4gICNkZWZpbmUJQ1dfUEVSX1BB R0UJCQk2Cj4gICNkZWZpbmUJVURfU0laRV9CWVRFUwkJCTkKPiArI2RlZmluZQlVRF9TSVpFX0JZ VEVTX01BU0sJCUdFTk1BU0soMTgsIDkpCj4gICNkZWZpbmUJRUNDX1BBUklUWV9TSVpFX0JZVEVT X1JTCTE5Cj4gICNkZWZpbmUJU1BBUkVfU0laRV9CWVRFUwkJMjMKPiArI2RlZmluZQlTUEFSRV9T SVpFX0JZVEVTX01BU0sJCUdFTk1BU0soMjYsIDIzKQo+ICAjZGVmaW5lCU5VTV9BRERSX0NZQ0xF UwkJCTI3Cj4gICNkZWZpbmUJU1RBVFVTX0JGUl9SRUFECQkJMzAKPiAgI2RlZmluZQlTRVRfUkRf TU9ERV9BRlRFUl9TVEFUVVMJMzEKPiBAQCAtMTAyLDYgKzEwNCw3IEBACj4gICNkZWZpbmUJRUND X01PREUJCQk0Cj4gICNkZWZpbmUJRUNDX1BBUklUWV9TSVpFX0JZVEVTX0JDSAk4Cj4gICNkZWZp bmUJRUNDX05VTV9EQVRBX0JZVEVTCQkxNgo+ICsjZGVmaW5lCUVDQ19OVU1fREFUQV9CWVRFU19N QVNLCQlHRU5NQVNLKDI1LCAxNikKPiAgI2RlZmluZQlFQ0NfRk9SQ0VfQ0xLX09QRU4JCTMwCj4g IAo+ICAvKiBOQU5EX0RFVl9DTUQxIGJpdHMgKi8KPiBAQCAtNDMxLDEzICs0MzQsMzIgQEAgc3Ry dWN0IHFjb21fbmFuZF9jb250cm9sbGVyIHsKPiAgCXUzMiBjbWQxLCB2bGQ7Cj4gIH07Cj4gIAo+ ICsvKgo+ICsgKiBOQU5EIHNwZWNpYWwgYm9vdCBwYXJ0aXRpb25zCj4gKyAqCj4gKyAqIEBwYWdl X29mZnNldDoJCW9mZnNldCBvZiB0aGUgcGFydGl0aW9uIHdoZXJlIHNwYXJlIGRhdGEgaXMgbm90 IHByb3RlY3RlZAo+ICsgKgkJCQlieSBFQ0MgKHZhbHVlIGluIHBhZ2VzKQo+ICsgKiBAcGFnZV9v ZmZzZXQ6CQlzaXplIG9mIHRoZSBwYXJ0aXRpb24gd2hlcmUgc3BhcmUgZGF0YSBpcyBub3QgcHJv dGVjdGVkCj4gKyAqCQkJCWJ5IEVDQyAodmFsdWUgaW4gcGFnZXMpCj4gKyAqLwo+ICtzdHJ1Y3Qg cWNvbV9uYW5kX2Jvb3RfcGFydGl0aW9uIHsKPiArCXUzMiBwYWdlX29mZnNldDsKPiArCXUzMiBw YWdlX3NpemU7Cj4gK307Cj4gKwo+ICAvKgo+ICAgKiBOQU5EIGNoaXAgc3RydWN0dXJlCj4gICAq Cj4gKyAqIEBib290X3BhcnRpdGlvbnM6CQlhcnJheSBvZiBib290IHBhcnRpdGlvbnMgd2hlcmUg b2Zmc2V0IGFuZCBzaXplIG9mIHRoZQo+ICsgKgkJCQlib290IHBhcnRpdGlvbnMgYXJlIHN0b3Jl ZAo+ICsgKgo+ICAgKiBAY2hpcDoJCQliYXNlIE5BTkQgY2hpcCBzdHJ1Y3R1cmUKPiAgICogQG5v ZGU6CQkJbGlzdCBub2RlIHRvIGFkZCBpdHNlbGYgdG8gaG9zdF9saXN0IGluCj4gICAqCQkJCXFj b21fbmFuZF9jb250cm9sbGVyCj4gICAqCj4gKyAqIEBucl9ib290X3BhcnRpdGlvbnM6CQljb3Vu dCBvZiB0aGUgYm9vdCBwYXJ0aXRpb25zIHdoZXJlIHNwYXJlIGRhdGEgaXMgbm90Cj4gKyAqCQkJ CXByb3RlY3RlZCBieSBFQ0MKPiArICoKPiAgICogQGNzOgkJCQljaGlwIHNlbGVjdCB2YWx1ZSBm b3IgdGhpcyBjaGlwCj4gICAqIEBjd19zaXplOgkJCXRoZSBudW1iZXIgb2YgYnl0ZXMgaW4gYSBz aW5nbGUgc3RlcC9jb2Rld29yZAo+ICAgKgkJCQlvZiBhIHBhZ2UsIGNvbnNpc3Rpbmcgb2YgYWxs IGRhdGEsIGVjYywgc3BhcmUKPiBAQCAtNDU2LDE0ICs0NzgsMjAgQEAgc3RydWN0IHFjb21fbmFu ZF9jb250cm9sbGVyIHsKPiAgICoKPiAgICogQHN0YXR1czoJCQl2YWx1ZSB0byBiZSByZXR1cm5l ZCBpZiBOQU5EX0NNRF9TVEFUVVMgY29tbWFuZAo+ICAgKgkJCQlpcyBleGVjdXRlZAo+ICsgKiBA Y29kZXdvcmRfZml4dXA6CQlrZWVwIHRyYWNrIG9mIHRoZSBjdXJyZW50IGxheW91dCB1c2VkIGJ5 Cj4gKyAqCQkJCXRoZSBkcml2ZXIgZm9yIHJlYWQvd3JpdGUgb3BlcmF0aW9uLgo+ICAgKiBAdXNl X2VjYzoJCQlyZXF1ZXN0IHRoZSBjb250cm9sbGVyIHRvIHVzZSBFQ0MgZm9yIHRoZQo+ICAgKgkJ CQl1cGNvbWluZyByZWFkL3dyaXRlCj4gICAqIEBiY2hfZW5hYmxlZDoJCWZsYWcgdG8gdGVsbCB3 aGV0aGVyIEJDSCBFQ0MgbW9kZSBpcyB1c2VkCj4gICAqLwo+ICBzdHJ1Y3QgcWNvbV9uYW5kX2hv c3Qgewo+ICsJc3RydWN0IHFjb21fbmFuZF9ib290X3BhcnRpdGlvbiAqYm9vdF9wYXJ0aXRpb25z Owo+ICsKPiAgCXN0cnVjdCBuYW5kX2NoaXAgY2hpcDsKPiAgCXN0cnVjdCBsaXN0X2hlYWQgbm9k ZTsKPiAgCj4gKwlpbnQgbnJfYm9vdF9wYXJ0aXRpb25zOwo+ICsKPiAgCWludCBjczsKPiAgCWlu dCBjd19zaXplOwo+ICAJaW50IGN3X2RhdGE7Cj4gQEAgLTQ4MSw2ICs1MDksNyBAQCBzdHJ1Y3Qg cWNvbV9uYW5kX2hvc3Qgewo+ICAJdTMyIGNscnJlYWRzdGF0dXM7Cj4gIAo+ICAJdTggc3RhdHVz Owo+ICsJYm9vbCBjb2Rld29yZF9maXh1cDsKPiAgCWJvb2wgdXNlX2VjYzsKPiAgCWJvb2wgYmNo X2VuYWJsZWQ7Cj4gIH07Cj4gQEAgLTQ5Myw2ICs1MjIsNyBAQCBzdHJ1Y3QgcWNvbV9uYW5kX2hv c3Qgewo+ICAgKiBAaXNfYmFtIC0gd2hldGhlciBOQU5EIGNvbnRyb2xsZXIgaXMgdXNpbmcgQkFN Cj4gICAqIEBpc19xcGljIC0gd2hldGhlciBOQU5EIENUUkwgaXMgcGFydCBvZiBxcGljIElQCj4g ICAqIEBxcGljX3YyIC0gZmxhZyB0byBpbmRpY2F0ZSBRUElDIElQIHZlcnNpb24gMgo+ICsgKiBA dXNlX2NvZGV3b3JkX2ZpeHVwIC0gd2hldGhlciBOQU5EIGhhcyBkaWZmZXJlbnQgbGF5b3V0IGZv ciBib290IHBhcnRpdGlvbnMKPiAgICovCj4gIHN0cnVjdCBxY29tX25hbmRjX3Byb3BzIHsKPiAg CXUzMiBlY2NfbW9kZXM7Cj4gQEAgLTUwMCw2ICs1MzAsNyBAQCBzdHJ1Y3QgcWNvbV9uYW5kY19w cm9wcyB7Cj4gIAlib29sIGlzX2JhbTsKPiAgCWJvb2wgaXNfcXBpYzsKPiAgCWJvb2wgcXBpY192 MjsKPiArCWJvb2wgdXNlX2NvZGV3b3JkX2ZpeHVwOwo+ICB9Owo+ICAKPiAgLyogRnJlZXMgdGhl IEJBTSB0cmFuc2FjdGlvbiBtZW1vcnkgKi8KPiBAQCAtMTcxOCw3ICsxNzQ5LDcgQEAgcWNvbV9u YW5kY19yZWFkX2N3X3JhdyhzdHJ1Y3QgbXRkX2luZm8gKm10ZCwgc3RydWN0IG5hbmRfY2hpcCAq Y2hpcCwKPiAgCWRhdGFfc2l6ZTEgPSBtdGQtPndyaXRlc2l6ZSAtIGhvc3QtPmN3X3NpemUgKiAo ZWNjLT5zdGVwcyAtIDEpOwo+ICAJb29iX3NpemUxID0gaG9zdC0+YmJtX3NpemU7Cj4gIAo+IC0J aWYgKHFjb21fbmFuZGNfaXNfbGFzdF9jdyhlY2MsIGN3KSkgewo+ICsJaWYgKHFjb21fbmFuZGNf aXNfbGFzdF9jdyhlY2MsIGN3KSAmJiAhaG9zdC0+Y29kZXdvcmRfZml4dXApIHsKPiAgCQlkYXRh X3NpemUyID0gZWNjLT5zaXplIC0gZGF0YV9zaXplMSAtCj4gIAkJCSAgICAgKChlY2MtPnN0ZXBz IC0gMSkgKiA0KTsKPiAgCQlvb2Jfc2l6ZTIgPSAoZWNjLT5zdGVwcyAqIDQpICsgaG9zdC0+ZWNj X2J5dGVzX2h3ICsKPiBAQCAtMTc5OSw3ICsxODMwLDcgQEAgY2hlY2tfZm9yX2VyYXNlZF9wYWdl KHN0cnVjdCBxY29tX25hbmRfaG9zdCAqaG9zdCwgdTggKmRhdGFfYnVmLAo+ICAJfQo+ICAKPiAg CWZvcl9lYWNoX3NldF9iaXQoY3csICZ1bmNvcnJlY3RhYmxlX2N3cywgZWNjLT5zdGVwcykgewo+ IC0JCWlmIChxY29tX25hbmRjX2lzX2xhc3RfY3coZWNjLCBjdykpIHsKPiArCQlpZiAocWNvbV9u YW5kY19pc19sYXN0X2N3KGVjYywgY3cpICYmICFob3N0LT5jb2Rld29yZF9maXh1cCkgewo+ICAJ CQlkYXRhX3NpemUgPSBlY2MtPnNpemUgLSAoKGVjYy0+c3RlcHMgLSAxKSAqIDQpOwo+ICAJCQlv b2Jfc2l6ZSA9IChlY2MtPnN0ZXBzICogNCkgKyBob3N0LT5lY2NfYnl0ZXNfaHc7Cj4gIAkJfSBl bHNlIHsKPiBAQCAtMTk1Nyw3ICsxOTg4LDcgQEAgc3RhdGljIGludCByZWFkX3BhZ2VfZWNjKHN0 cnVjdCBxY29tX25hbmRfaG9zdCAqaG9zdCwgdTggKmRhdGFfYnVmLAo+ICAJZm9yIChpID0gMDsg aSA8IGVjYy0+c3RlcHM7IGkrKykgewo+ICAJCWludCBkYXRhX3NpemUsIG9vYl9zaXplOwo+ICAK PiAtCQlpZiAocWNvbV9uYW5kY19pc19sYXN0X2N3KGVjYywgaSkpIHsKPiArCQlpZiAocWNvbV9u YW5kY19pc19sYXN0X2N3KGVjYywgaSkgJiYgIWhvc3QtPmNvZGV3b3JkX2ZpeHVwKSB7Cj4gIAkJ CWRhdGFfc2l6ZSA9IGVjYy0+c2l6ZSAtICgoZWNjLT5zdGVwcyAtIDEpIDw8IDIpOwo+ICAJCQlv b2Jfc2l6ZSA9IChlY2MtPnN0ZXBzIDw8IDIpICsgaG9zdC0+ZWNjX2J5dGVzX2h3ICsKPiAgCQkJ CSAgIGhvc3QtPnNwYXJlX2J5dGVzOwo+IEBAIC0yMDU0LDYgKzIwODUsNjkgQEAgc3RhdGljIGlu dCBjb3B5X2xhc3RfY3coc3RydWN0IHFjb21fbmFuZF9ob3N0ICpob3N0LCBpbnQgcGFnZSkKPiAg CXJldHVybiByZXQ7Cj4gIH0KPiAgCj4gK3N0YXRpYyBib29sIHFjb21fbmFuZGNfaXNfYm9vdF9w YXJ0aXRpb24oc3RydWN0IHFjb21fbmFuZF9ob3N0ICpob3N0LCBpbnQgcGFnZSkKPiArewo+ICsJ c3RydWN0IHFjb21fbmFuZF9ib290X3BhcnRpdGlvbiAqYm9vdF9wYXJ0aXRpb247Cj4gKwl1MzIg c3RhcnQsIGVuZDsKPiArCWludCBpOwo+ICsKPiArCS8qCj4gKwkgKiBTaW5jZSB0aGUgZnJlcXVl bnQgYWNjZXNzIHdpbGwgYmUgdG8gdGhlIG5vbi1ib290IHBhcnRpdGlvbnMgbGlrZSByb290ZnMs Cj4gKwkgKiBvcHRpbWl6ZSB0aGUgcGFnZSBjaGVjayBieToKPiArCSAqCj4gKwkgKiAxLiBDaGVj a2luZyBpZiB0aGUgcGFnZSBsaWVzIGFmdGVyIHRoZSBsYXN0IGJvb3QgcGFydGl0aW9uLgo+ICsJ ICogMi4gQ2hlY2tpbmcgZnJvbSB0aGUgYm9vdCBwYXJ0aXRpb24gZW5kLgo+ICsJICovCj4gKwo+ ICsJLyogRmlyc3QgY2hlY2sgdGhlIGxhc3QgYm9vdCBwYXJ0aXRpb24gKi8KPiArCWJvb3RfcGFy dGl0aW9uID0gJmhvc3QtPmJvb3RfcGFydGl0aW9uc1tob3N0LT5ucl9ib290X3BhcnRpdGlvbnMg LSAxXTsKPiArCXN0YXJ0ID0gYm9vdF9wYXJ0aXRpb24tPnBhZ2Vfb2Zmc2V0Owo+ICsJZW5kID0g c3RhcnQgKyBib290X3BhcnRpdGlvbi0+cGFnZV9zaXplOwo+ICsKPiArCS8qIFBhZ2UgaXMgYWZ0 ZXIgdGhlIGxhc3QgYm9vdCBwYXJ0aXRpb24gZW5kLiBUaGlzIGlzIE5PVCBhIGJvb3QgcGFydGl0 aW9uICovCj4gKwlpZiAocGFnZSA+IGVuZCkKPiArCQlyZXR1cm4gZmFsc2U7Cj4gKwo+ICsJLyog QWN0dWFsbHkgY2hlY2sgaWYgaXQncyBhIGJvb3QgcGFydGl0aW9uICovCj4gKwlpZiAocGFnZSA8 IGVuZCAmJiBwYWdlID49IHN0YXJ0KQo+ICsJCXJldHVybiB0cnVlOwo+ICsKPiArCS8qIENoZWNr IHRoZSBvdGhlciBib290IHBhcnRpdGlvbnMgc3RhcnRpbmcgZnJvbSB0aGUgc2Vjb25kLWxhc3Qg cGFydGl0aW9uICovCj4gKwlmb3IgKGkgPSBob3N0LT5ucl9ib290X3BhcnRpdGlvbnMgLSAyOyBp ID49IDA7IGktLSkgewo+ICsJCWJvb3RfcGFydGl0aW9uID0gJmhvc3QtPmJvb3RfcGFydGl0aW9u c1tpXTsKPiArCQlzdGFydCA9IGJvb3RfcGFydGl0aW9uLT5wYWdlX29mZnNldDsKPiArCQllbmQg PSBzdGFydCArIGJvb3RfcGFydGl0aW9uLT5wYWdlX3NpemU7Cj4gKwo+ICsJCWlmIChwYWdlIDwg ZW5kICYmIHBhZ2UgPj0gc3RhcnQpCj4gKwkJCXJldHVybiB0cnVlOwo+ICsJfQo+ICsKPiArCXJl dHVybiBmYWxzZTsKPiArfQo+ICsKPiArc3RhdGljIHZvaWQgcWNvbV9uYW5kY19jb2Rld29yZF9m aXh1cChzdHJ1Y3QgcWNvbV9uYW5kX2hvc3QgKmhvc3QsIGludCBwYWdlKQo+ICt7Cj4gKwlib29s IGNvZGV3b3JkX2ZpeHVwID0gcWNvbV9uYW5kY19pc19ib290X3BhcnRpdGlvbihob3N0LCBwYWdl KTsKPiArCj4gKwkvKiBTa2lwIGNvbmYgd3JpdGUgaWYgd2UgYXJlIGFscmVhZHkgaW4gdGhlIGNv cnJlY3QgbW9kZSAqLwo+ICsJaWYgKGNvZGV3b3JkX2ZpeHVwID09IGhvc3QtPmNvZGV3b3JkX2Zp eHVwKQo+ICsJCXJldHVybjsKPiArCj4gKwlob3N0LT5jb2Rld29yZF9maXh1cCA9IGNvZGV3b3Jk X2ZpeHVwOwo+ICsKPiArCWhvc3QtPmN3X2RhdGEgPSBjb2Rld29yZF9maXh1cCA/IDUxMiA6IDUx NjsKPiArCWhvc3QtPnNwYXJlX2J5dGVzID0gaG9zdC0+Y3dfc2l6ZSAtIGhvc3QtPmVjY19ieXRl c19odyAtCj4gKwkJCSAgICBob3N0LT5iYm1fc2l6ZSAtIGhvc3QtPmN3X2RhdGE7Cj4gKwo+ICsJ aG9zdC0+Y2ZnMCAmPSB+KFNQQVJFX1NJWkVfQllURVNfTUFTSyB8IFVEX1NJWkVfQllURVNfTUFT Syk7Cj4gKwlob3N0LT5jZmcwIHw9IGhvc3QtPnNwYXJlX2J5dGVzIDw8IFNQQVJFX1NJWkVfQllU RVMgfAo+ICsJCSAgICAgIGhvc3QtPmN3X2RhdGEgPDwgVURfU0laRV9CWVRFUzsKPiArCj4gKwlo b3N0LT5lY2NfYmNoX2NmZyAmPSB+RUNDX05VTV9EQVRBX0JZVEVTX01BU0s7Cj4gKwlob3N0LT5l Y2NfYmNoX2NmZyB8PSBob3N0LT5jd19kYXRhIDw8IEVDQ19OVU1fREFUQV9CWVRFUzsKPiArCWhv c3QtPmVjY19idWZfY2ZnID0gKGhvc3QtPmN3X2RhdGEgLSAxKSA8PCBOVU1fU1RFUFM7Cj4gK30K PiArCj4gIC8qIGltcGxlbWVudHMgZWNjLT5yZWFkX3BhZ2UoKSAqLwo+ICBzdGF0aWMgaW50IHFj b21fbmFuZGNfcmVhZF9wYWdlKHN0cnVjdCBuYW5kX2NoaXAgKmNoaXAsIHVpbnQ4X3QgKmJ1ZiwK PiAgCQkJCWludCBvb2JfcmVxdWlyZWQsIGludCBwYWdlKQo+IEBAIC0yMDYyLDYgKzIxNTYsOSBA QCBzdGF0aWMgaW50IHFjb21fbmFuZGNfcmVhZF9wYWdlKHN0cnVjdCBuYW5kX2NoaXAgKmNoaXAs IHVpbnQ4X3QgKmJ1ZiwKPiAgCXN0cnVjdCBxY29tX25hbmRfY29udHJvbGxlciAqbmFuZGMgPSBn ZXRfcWNvbV9uYW5kX2NvbnRyb2xsZXIoY2hpcCk7Cj4gIAl1OCAqZGF0YV9idWYsICpvb2JfYnVm ID0gTlVMTDsKPiAgCj4gKwlpZiAoaG9zdC0+bnJfYm9vdF9wYXJ0aXRpb25zKQo+ICsJCXFjb21f bmFuZGNfY29kZXdvcmRfZml4dXAoaG9zdCwgcGFnZSk7Cj4gKwo+ICAJbmFuZF9yZWFkX3BhZ2Vf b3AoY2hpcCwgcGFnZSwgMCwgTlVMTCwgMCk7Cj4gIAlkYXRhX2J1ZiA9IGJ1ZjsKPiAgCW9vYl9i dWYgPSBvb2JfcmVxdWlyZWQgPyBjaGlwLT5vb2JfcG9pIDogTlVMTDsKPiBAQCAtMjA4MSw2ICsy MTc4LDkgQEAgc3RhdGljIGludCBxY29tX25hbmRjX3JlYWRfcGFnZV9yYXcoc3RydWN0IG5hbmRf Y2hpcCAqY2hpcCwgdWludDhfdCAqYnVmLAo+ICAJaW50IGN3LCByZXQ7Cj4gIAl1OCAqZGF0YV9i dWYgPSBidWYsICpvb2JfYnVmID0gY2hpcC0+b29iX3BvaTsKPiAgCj4gKwlpZiAoaG9zdC0+bnJf Ym9vdF9wYXJ0aXRpb25zKQo+ICsJCXFjb21fbmFuZGNfY29kZXdvcmRfZml4dXAoaG9zdCwgcGFn ZSk7Cj4gKwo+ICAJZm9yIChjdyA9IDA7IGN3IDwgZWNjLT5zdGVwczsgY3crKykgewo+ICAJCXJl dCA9IHFjb21fbmFuZGNfcmVhZF9jd19yYXcobXRkLCBjaGlwLCBkYXRhX2J1Ziwgb29iX2J1ZiwK PiAgCQkJCQkgICAgIHBhZ2UsIGN3KTsKPiBAQCAtMjEwMSw2ICsyMjAxLDkgQEAgc3RhdGljIGlu dCBxY29tX25hbmRjX3JlYWRfb29iKHN0cnVjdCBuYW5kX2NoaXAgKmNoaXAsIGludCBwYWdlKQo+ ICAJc3RydWN0IHFjb21fbmFuZF9jb250cm9sbGVyICpuYW5kYyA9IGdldF9xY29tX25hbmRfY29u dHJvbGxlcihjaGlwKTsKPiAgCXN0cnVjdCBuYW5kX2VjY19jdHJsICplY2MgPSAmY2hpcC0+ZWNj Owo+ICAKPiArCWlmIChob3N0LT5ucl9ib290X3BhcnRpdGlvbnMpCj4gKwkJcWNvbV9uYW5kY19j b2Rld29yZF9maXh1cChob3N0LCBwYWdlKTsKPiArCj4gIAljbGVhcl9yZWFkX3JlZ3MobmFuZGMp Owo+ICAJY2xlYXJfYmFtX3RyYW5zYWN0aW9uKG5hbmRjKTsKPiAgCj4gQEAgLTIxMjEsNiArMjIy NCw5IEBAIHN0YXRpYyBpbnQgcWNvbV9uYW5kY193cml0ZV9wYWdlKHN0cnVjdCBuYW5kX2NoaXAg KmNoaXAsIGNvbnN0IHVpbnQ4X3QgKmJ1ZiwKPiAgCXU4ICpkYXRhX2J1ZiwgKm9vYl9idWY7Cj4g IAlpbnQgaSwgcmV0Owo+ICAKPiArCWlmIChob3N0LT5ucl9ib290X3BhcnRpdGlvbnMpCj4gKwkJ cWNvbV9uYW5kY19jb2Rld29yZF9maXh1cChob3N0LCBwYWdlKTsKPiArCj4gIAluYW5kX3Byb2df cGFnZV9iZWdpbl9vcChjaGlwLCBwYWdlLCAwLCBOVUxMLCAwKTsKPiAgCj4gIAljbGVhcl9yZWFk X3JlZ3MobmFuZGMpOwo+IEBAIC0yMTM2LDcgKzIyNDIsNyBAQCBzdGF0aWMgaW50IHFjb21fbmFu ZGNfd3JpdGVfcGFnZShzdHJ1Y3QgbmFuZF9jaGlwICpjaGlwLCBjb25zdCB1aW50OF90ICpidWYs Cj4gIAlmb3IgKGkgPSAwOyBpIDwgZWNjLT5zdGVwczsgaSsrKSB7Cj4gIAkJaW50IGRhdGFfc2l6 ZSwgb29iX3NpemU7Cj4gIAo+IC0JCWlmIChxY29tX25hbmRjX2lzX2xhc3RfY3coZWNjLCBpKSkg ewo+ICsJCWlmIChxY29tX25hbmRjX2lzX2xhc3RfY3coZWNjLCBpKSAmJiAhaG9zdC0+Y29kZXdv cmRfZml4dXApIHsKPiAgCQkJZGF0YV9zaXplID0gZWNjLT5zaXplIC0gKChlY2MtPnN0ZXBzIC0g MSkgPDwgMik7Cj4gIAkJCW9vYl9zaXplID0gKGVjYy0+c3RlcHMgPDwgMikgKyBob3N0LT5lY2Nf Ynl0ZXNfaHcgKwo+ICAJCQkJICAgaG9zdC0+c3BhcmVfYnl0ZXM7Cj4gQEAgLTIxOTMsNiArMjI5 OSw5IEBAIHN0YXRpYyBpbnQgcWNvbV9uYW5kY193cml0ZV9wYWdlX3JhdyhzdHJ1Y3QgbmFuZF9j aGlwICpjaGlwLAo+ICAJdTggKmRhdGFfYnVmLCAqb29iX2J1ZjsKPiAgCWludCBpLCByZXQ7Cj4g IAo+ICsJaWYgKGhvc3QtPm5yX2Jvb3RfcGFydGl0aW9ucykKPiArCQlxY29tX25hbmRjX2NvZGV3 b3JkX2ZpeHVwKGhvc3QsIHBhZ2UpOwo+ICsKPiAgCW5hbmRfcHJvZ19wYWdlX2JlZ2luX29wKGNo aXAsIHBhZ2UsIDAsIE5VTEwsIDApOwo+ICAJY2xlYXJfcmVhZF9yZWdzKG5hbmRjKTsKPiAgCWNs ZWFyX2JhbV90cmFuc2FjdGlvbihuYW5kYyk7Cj4gQEAgLTIyMTEsNyArMjMyMCw3IEBAIHN0YXRp YyBpbnQgcWNvbV9uYW5kY193cml0ZV9wYWdlX3JhdyhzdHJ1Y3QgbmFuZF9jaGlwICpjaGlwLAo+ ICAJCWRhdGFfc2l6ZTEgPSBtdGQtPndyaXRlc2l6ZSAtIGhvc3QtPmN3X3NpemUgKiAoZWNjLT5z dGVwcyAtIDEpOwo+ICAJCW9vYl9zaXplMSA9IGhvc3QtPmJibV9zaXplOwo+ICAKPiAtCQlpZiAo cWNvbV9uYW5kY19pc19sYXN0X2N3KGVjYywgaSkpIHsKPiArCQlpZiAocWNvbV9uYW5kY19pc19s YXN0X2N3KGVjYywgaSkgJiYgIWhvc3QtPmNvZGV3b3JkX2ZpeHVwKSB7Cj4gIAkJCWRhdGFfc2l6 ZTIgPSBlY2MtPnNpemUgLSBkYXRhX3NpemUxIC0KPiAgCQkJCSAgICAgKChlY2MtPnN0ZXBzIC0g MSkgPDwgMik7Cj4gIAkJCW9vYl9zaXplMiA9IChlY2MtPnN0ZXBzIDw8IDIpICsgaG9zdC0+ZWNj X2J5dGVzX2h3ICsKPiBAQCAtMjI3MSw2ICsyMzgwLDkgQEAgc3RhdGljIGludCBxY29tX25hbmRj X3dyaXRlX29vYihzdHJ1Y3QgbmFuZF9jaGlwICpjaGlwLCBpbnQgcGFnZSkKPiAgCWludCBkYXRh X3NpemUsIG9vYl9zaXplOwo+ICAJaW50IHJldDsKPiAgCj4gKwlpZiAoaG9zdC0+bnJfYm9vdF9w YXJ0aXRpb25zKQo+ICsJCXFjb21fbmFuZGNfY29kZXdvcmRfZml4dXAoaG9zdCwgcGFnZSk7Cj4g Kwo+ICAJaG9zdC0+dXNlX2VjYyA9IHRydWU7Cj4gIAljbGVhcl9iYW1fdHJhbnNhY3Rpb24obmFu ZGMpOwo+ICAKPiBAQCAtMjkxOSw2ICszMDMxLDc0IEBAIHN0YXRpYyBpbnQgcWNvbV9uYW5kY19z ZXR1cChzdHJ1Y3QgcWNvbV9uYW5kX2NvbnRyb2xsZXIgKm5hbmRjKQo+ICAKPiAgc3RhdGljIGNv bnN0IGNoYXIgKiBjb25zdCBwcm9iZXNbXSA9IHsgImNtZGxpbmVwYXJ0IiwgIm9mcGFydCIsICJx Y29tc21lbSIsIE5VTEwgfTsKPiAgCj4gK3N0YXRpYyBpbnQgcWNvbV9uYW5kX2hvc3RfcGFyc2Vf Ym9vdF9wYXJ0aXRpb25zKHN0cnVjdCBxY29tX25hbmRfY29udHJvbGxlciAqbmFuZGMsCj4gKwkJ CQkJCXN0cnVjdCBxY29tX25hbmRfaG9zdCAqaG9zdCwKPiArCQkJCQkJc3RydWN0IGRldmljZV9u b2RlICpkbikKPiArewo+ICsJc3RydWN0IG5hbmRfY2hpcCAqY2hpcCA9ICZob3N0LT5jaGlwOwo+ ICsJc3RydWN0IG10ZF9pbmZvICptdGQgPSBuYW5kX3RvX210ZChjaGlwKTsKPiArCXN0cnVjdCBx Y29tX25hbmRfYm9vdF9wYXJ0aXRpb24gKmJvb3RfcGFydGl0aW9uOwo+ICsJc3RydWN0IGRldmlj ZSAqZGV2ID0gbmFuZGMtPmRldjsKPiArCWludCBwYXJ0aXRpb25zX2NvdW50LCBpLCBqLCByZXQ7 Cj4gKwo+ICsJaWYgKCFvZl9maW5kX3Byb3BlcnR5KGRuLCAicWNvbSxib290LXBhcnRpdGlvbnMi LCBOVUxMKSkKPiArCQlyZXR1cm4gMDsKPiArCj4gKwlwYXJ0aXRpb25zX2NvdW50ID0gb2ZfcHJv cGVydHlfY291bnRfdTMyX2VsZW1zKGRuLCAicWNvbSxib290LXBhcnRpdGlvbnMiKTsKPiArCWlm IChwYXJ0aXRpb25zX2NvdW50IDw9IDApIHsKPiArCQlkZXZfZXJyKGRldiwgIkVycm9yIHBhcnNp bmcgYm9vdCBwYXJ0aXRpb25cbiIpOwo+ICsJCXJldHVybiBwYXJ0aXRpb25zX2NvdW50ID8gcGFy dGl0aW9uc19jb3VudCA6IC1FSU5WQUw7Cj4gKwl9Cj4gKwo+ICsJaG9zdC0+bnJfYm9vdF9wYXJ0 aXRpb25zID0gcGFydGl0aW9uc19jb3VudCAvIDI7Cj4gKwlob3N0LT5ib290X3BhcnRpdGlvbnMg PSBkZXZtX2tjYWxsb2MoZGV2LCBob3N0LT5ucl9ib290X3BhcnRpdGlvbnMsCj4gKwkJCQkJICAg ICBzaXplb2YoKmhvc3QtPmJvb3RfcGFydGl0aW9ucyksIEdGUF9LRVJORUwpOwo+ICsJaWYgKCFo b3N0LT5ib290X3BhcnRpdGlvbnMpIHsKPiArCQlob3N0LT5ucl9ib290X3BhcnRpdGlvbnMgPSAw Owo+ICsJCXJldHVybiAtRU5PTUVNOwo+ICsJfQo+ICsKPiArCWZvciAoaSA9IDAsIGogPSAwOyBp IDwgaG9zdC0+bnJfYm9vdF9wYXJ0aXRpb25zOyBpKyssIGogKz0gMikgewo+ICsJCWJvb3RfcGFy dGl0aW9uID0gJmhvc3QtPmJvb3RfcGFydGl0aW9uc1tpXTsKPiArCj4gKwkJcmV0ID0gb2ZfcHJv cGVydHlfcmVhZF91MzJfaW5kZXgoZG4sICJxY29tLGJvb3QtcGFydGl0aW9ucyIsIGosCj4gKwkJ CQkJCSAmYm9vdF9wYXJ0aXRpb24tPnBhZ2Vfb2Zmc2V0KTsKPiArCQlpZiAocmV0KSB7Cj4gKwkJ CWRldl9lcnIoZGV2LCAiRXJyb3IgcGFyc2luZyBib290IHBhcnRpdGlvbiBvZmZzZXQgYXQgaW5k ZXggJWRcbiIsIGkpOwo+ICsJCQlob3N0LT5ucl9ib290X3BhcnRpdGlvbnMgPSAwOwo+ICsJCQly ZXR1cm4gcmV0Owo+ICsJCX0KPiArCj4gKwkJaWYgKGJvb3RfcGFydGl0aW9uLT5wYWdlX29mZnNl dCAlIG10ZC0+d3JpdGVzaXplKSB7Cj4gKwkJCWRldl9lcnIoZGV2LCAiQm9vdCBwYXJ0aXRpb24g b2Zmc2V0IG5vdCBtdWx0aXBsZSBvZiB3cml0ZXNpemUgYXQgaW5kZXggJWlcbiIsCj4gKwkJCQlp KTsKPiArCQkJaG9zdC0+bnJfYm9vdF9wYXJ0aXRpb25zID0gMDsKPiArCQkJcmV0dXJuIC1FSU5W QUw7Cj4gKwkJfQo+ICsJCS8qIENvbnZlcnQgb2Zmc2V0IHRvIG5hbmQgcGFnZXMgKi8KPiArCQli b290X3BhcnRpdGlvbi0+cGFnZV9vZmZzZXQgLz0gbXRkLT53cml0ZXNpemU7Cj4gKwo+ICsJCXJl dCA9IG9mX3Byb3BlcnR5X3JlYWRfdTMyX2luZGV4KGRuLCAicWNvbSxib290LXBhcnRpdGlvbnMi LCBqICsgMSwKPiArCQkJCQkJICZib290X3BhcnRpdGlvbi0+cGFnZV9zaXplKTsKPiArCQlpZiAo cmV0KSB7Cj4gKwkJCWRldl9lcnIoZGV2LCAiRXJyb3IgcGFyc2luZyBib290IHBhcnRpdGlvbiBz aXplIGF0IGluZGV4ICVkXG4iLCBpKTsKPiArCQkJaG9zdC0+bnJfYm9vdF9wYXJ0aXRpb25zID0g MDsKPiArCQkJcmV0dXJuIHJldDsKPiArCQl9Cj4gKwo+ICsJCWlmIChib290X3BhcnRpdGlvbi0+ cGFnZV9zaXplICUgbXRkLT53cml0ZXNpemUpIHsKPiArCQkJZGV2X2VycihkZXYsICJCb290IHBh cnRpdGlvbiBzaXplIG5vdCBtdWx0aXBsZSBvZiB3cml0ZXNpemUgYXQgaW5kZXggJWlcbiIsCj4g KwkJCQlpKTsKPiArCQkJaG9zdC0+bnJfYm9vdF9wYXJ0aXRpb25zID0gMDsKPiArCQkJcmV0dXJu IC1FSU5WQUw7Cj4gKwkJfQo+ICsJCS8qIENvbnZlcnQgc2l6ZSB0byBuYW5kIHBhZ2VzICovCj4g KwkJYm9vdF9wYXJ0aXRpb24tPnBhZ2Vfc2l6ZSAvPSBtdGQtPndyaXRlc2l6ZTsKPiArCX0KPiAr Cj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiAgc3RhdGljIGludCBxY29tX25hbmRfaG9zdF9pbml0 X2FuZF9yZWdpc3RlcihzdHJ1Y3QgcWNvbV9uYW5kX2NvbnRyb2xsZXIgKm5hbmRjLAo+ICAJCQkJ CSAgICBzdHJ1Y3QgcWNvbV9uYW5kX2hvc3QgKmhvc3QsCj4gIAkJCQkJICAgIHN0cnVjdCBkZXZp Y2Vfbm9kZSAqZG4pCj4gQEAgLTI5ODcsNiArMzE2NywxNCBAQCBzdGF0aWMgaW50IHFjb21fbmFu ZF9ob3N0X2luaXRfYW5kX3JlZ2lzdGVyKHN0cnVjdCBxY29tX25hbmRfY29udHJvbGxlciAqbmFu ZGMsCj4gIAlpZiAocmV0KQo+ICAJCW5hbmRfY2xlYW51cChjaGlwKTsKPiAgCj4gKwlpZiAobmFu ZGMtPnByb3BzLT51c2VfY29kZXdvcmRfZml4dXApIHsKPiArCQlyZXQgPSBxY29tX25hbmRfaG9z dF9wYXJzZV9ib290X3BhcnRpdGlvbnMobmFuZGMsIGhvc3QsIGRuKTsKPiArCQlpZiAocmV0KSB7 Cj4gKwkJCW5hbmRfY2xlYW51cChjaGlwKTsKPiArCQkJcmV0dXJuIHJldDsKPiArCQl9Cj4gKwl9 Cj4gKwo+ICAJcmV0dXJuIHJldDsKPiAgfQo+ICAKPiBAQCAtMzE1Miw2ICszMzQwLDcgQEAgc3Rh dGljIGludCBxY29tX25hbmRjX3JlbW92ZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQo+ ICBzdGF0aWMgY29uc3Qgc3RydWN0IHFjb21fbmFuZGNfcHJvcHMgaXBxODA2eF9uYW5kY19wcm9w cyA9IHsKPiAgCS5lY2NfbW9kZXMgPSAoRUNDX1JTXzRCSVQgfCBFQ0NfQkNIXzhCSVQpLAo+ICAJ LmlzX2JhbSA9IGZhbHNlLAo+ICsJLnVzZV9jb2Rld29yZF9maXh1cCA9IHRydWUsCj4gIAkuZGV2 X2NtZF9yZWdfc3RhcnQgPSAweDAsCj4gIH07Cj4gIAo+IC0tIAo+IDIuMzYuMQo+IAoKLS0gCuCu ruCuo+Cuv+CuteCuo+CvjeCuo+CuqeCvjSDgrprgrqTgrr7grprgrr/grrXgrq7gr40KCl9fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpMaW51eCBN VEQgZGlzY3Vzc2lvbiBtYWlsaW5nIGxpc3QKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFp bG1hbi9saXN0aW5mby9saW51eC1tdGQvCg==