From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DF536C433EF for ; Thu, 23 Jun 2022 14:42:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DOv8jFbh7XLMq8eKvftMo2My5xX7hC38lN/dS5nZA5c=; b=RlLnhxsILJl46Y fRMkXC1oRYEAJyMi3ja4sNUPHDg/ZlPRcgEMcUi/jIP8LU42+OxzuO3RkeTIj0i3KVeG1MwervO99 jZXEuCmCQMZQcqbmFh1badU9R4JUunZjpbkpok4YMjQVjhMiwnwPC5MdG8A/NwV1CLIBKddrU8Yeu 8AFcI5eJPV5l+dBpnw2bAimpXp4TVQflyqxqd10a5CU0ZsRWAftlQoyJAyo5LdP3yyOcsfVHIiov+ WcxnVHclSu4znppYm/wS2T0n+al+spBMqXVuP+iCvURMzQvAX221s9t+cz/E06eXF8QsJv8OQ67c/ dbMIVPR+J/1jWLUJnBTw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o4O1q-00FZ2N-Le; Thu, 23 Jun 2022 14:41:54 +0000 Received: from mickerik.phytec.de ([195.145.39.210]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o4O1X-00FYtm-IB for linux-arm-kernel@lists.infradead.org; Thu, 23 Jun 2022 14:41:38 +0000 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1655995285; x=1658587285; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=1Ny/IhS26LkyjgL1J8uUWi3R9TUW1Za6jMAEjBfF5qw=; b=tZJ0/z16Czm9x8hAfZSkxaW4BNMkCCexx8LTSUVuPrtsMVOfz9nl3M5uovdLdHnf m69BO2C/U4n55qKowfbJ4N+ANqaGz88H4VQ71h8MTUI3/wKPIEEHF1XFa8+/FkWk CKYSw7bdqr3I3X80q88ssl2wl1bB3Bx4a9LYSvBgAZw=; X-AuditID: c39127d2-b3a2d70000001dbe-bd-62b47b95290a Received: from idefix.phytec.de (Unknown_Domain [172.25.0.20]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 23.50.07614.59B74B26; Thu, 23 Jun 2022 16:41:25 +0200 (CEST) Received: from augenblix2.phytec.de ([172.25.0.51]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2022062316412515-228336 ; Thu, 23 Jun 2022 16:41:25 +0200 From: Teresa Remmet To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Fabio Estevam , NXP Linux Team , Sascha Hauer , upstream@phytec.de Subject: [PATCH v4 3/3] arm64: dts: freescale: Add phyBOARD-Polis-i.MX8MM support Date: Thu, 23 Jun 2022 16:41:24 +0200 Message-Id: <20220623144124.1821570-3-t.remmet@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220623144124.1821570-1-t.remmet@phytec.de> References: <20220623144124.1821570-1-t.remmet@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 23.06.2022 16:41:25, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 23.06.2022 16:41:25 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrHLMWRmVeSWpSXmKPExsWyRpJBRHdq9ZYkg3NHZSzmHznHavHwqr9F 34uHzBabHl9jtej6tZLZonXvEXaLv9s3sVi82CLuwOGxc9Zddo9NqzrZPO5c28PmsXlJvcfG dzuYPPr/Gnh83iQXwB7FZZOSmpNZllqkb5fAlTGraStLwenbjBXt59qYGxgPbmXsYuTkkBAw kVjx4yBzFyMXh5DANkaJq03/GCGc84wSNx5MYAapYhPQkHi64jQTiC0i4CLR+WAdC0gRs0Aj k8SOYxfAioQFAiXuvd/IAmKzCKhKfJ/8FayBV8BS4vK66+wQ6+QlZl76DmZzClhJfN83FcwW AqpZ9foqM0S9oMTJmU/AFkgIXGGUODXhHzNEs5DE6cVnwWxmAW2JZQtfM09gFJiFpGcWktQC RqZVjEK5mcnZqUWZ2XoFGZUlqcl6KambGIFhfnii+qUdjH1zPA4xMnEwHmKU4GBWEuF98X9z khBvSmJlVWpRfnxRaU5q8SFGaQ4WJXHe+z1MiUIC6YklqdmpqQWpRTBZJg5OqQZGzj6+UK/N uvrVG730jG5yvZObWzNXjPcMwyczw+fNcnfbty9pFj9k3vivTY5NYU7htulHp0f4rJM58WjL v2YFw5clJotWHmtQCrK+c2il2fV0qflK/7VfxN/rZmF5Y/yKXaRU7pimREjb6+rMe9nle63O XGi8fUp5Dc+N+xkzemuuXk5cI+CvxFKckWioxVxUnAgAJIGED2ECAAA= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220623_074135_947666_17973AC5 X-CRM114-Status: GOOD ( 15.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add initial support for phyBOARD-Polis-i.MX8MM. Main features are: * Bluetooth and Wifi * CANFD * eMMC * i2c RTC * Ethernet * PCIe * RS232/RS485 * SD-Card * SPI-NOR flash * USB Signed-off-by: Teresa Remmet --- Changes in v4: - Do not modify reserved iomux bits - Remove eth phy irq due to a recent found hw issue on SoM Changes in v3: - move "enable-active-high" after "gpio" property - Add missing newlines before child nodes - sort i2c devices by address Changes in v2: - added missing space in compatible of imx8mm-phyboard-polis-rdk - removed underscores in node names - fixed indentation of reg_usdhc2_vmmc node - put status always as last property of nodes - updated node name of sn65dsi83 to bridge --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx8mm-phyboard-polis-rdk.dts | 450 ++++++++++++++++++ .../dts/freescale/imx8mm-phycore-som.dtsi | 440 +++++++++++++++++ 3 files changed, 891 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 238a83e5b8c6..1e25dec2109b 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -58,6 +58,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts new file mode 100644 index 000000000000..4a3df2b77b0b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +/dts-v1/; + +#include +#include +#include +#include "imx8mm-phycore-som.dtsi" + +/ { + model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK"; + compatible = "phytec,imx8mm-phyboard-polis-rdk", + "phytec,imx8mm-phycore-som", "fsl,imx8mm"; + + chosen { + stdout-path = &uart3; + }; + + bt_osc_32k: bt-lp-clock { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "bt_osc_32k"; + #clock-cells = <0>; + }; + + can_osc_40m: can-clock { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + clock-output-names = "can_osc_40m"; + #clock-cells = <0>; + }; + + fan { + compatible = "gpio-fan"; + gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 13000 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan>; + #cooling-cells = <2>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + color = ; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc2"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_CPU; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + usdhc1_pwrseq: pwr-seq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <60>; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_en>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "CAN_EN"; + startup-delay-us = <20>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1 { + compatible = "regulator-fixed"; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1pwrgrp>; + regulator-name = "usb_otg1_vbus"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <20000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + }; + + reg_vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC_3V3"; + }; +}; + +/* SPI - CAN MCP251XFD */ +&ecspi1 { + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp251xfd"; + clocks = <&can_osc_40m>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + spi-max-frequency = <20000000>; + xceiver-supply = <®_can_en>; + }; +}; + +&gpio1 { + gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT", + "", "", "", "RESET_ETHPHY", + "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "", + "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", + "", "", "BT_REG_ON", "WL_REG_ON", + "BT_DEV_WAKE", "BT_HOST_WAKE", "", "", + "X_SD2_CD_B", "", "", "", + "", "", "", "SD2_RESET_B"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "FAN", "miniPCIe_nPERST", "", "", + "COEX1", "COEX2"; +}; + +&gpio5 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "ECSPI1_SS0"; +}; + +/* PCIe */ +&pcie0 { + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + assigned-clock-rates = <10000000>, <250000000>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie_phy { + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + status = "okay"; +}; + +&rv3028 { + trickle-resistor-ohms = <3000>; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* UART - RS232/RS485 */ +&uart1 { + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +/* UART - Sterling-LWB Bluetooth */ +&uart2 { + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_bt>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&bt_osc_32k>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wakeup"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_EDGE_BOTH>; + max-speed = <2000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt>; + shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + vddio-supply = <®_vcc_3v3>; + }; +}; + +/* UART - console */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* USB */ +&usbotg1 { + adp-disable; + dr_mode = "otg"; + over-current-active-low; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + srp-disable; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; +}; + +/* SDIO - Sterling-LWB Wifi */ +&usdhc1 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + mmc-pwrseq = <&usdhc1_pwrseq>; + non-removable; + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +/* SD-Card */ +&usdhc2 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_nvcc_sd2>; + status = "okay"; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00 + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00 + >; + }; + + pinctrl_can_en: can-engrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 + >; + }; + + pinctrl_can_int: can-intgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 + >; + }; + + pinctrl_fan: fan0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16 + >; + }; + + pinctrl_leds: leds1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16 + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00 + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00 + >; + }; + + pinctrl_uart2_bt: uart2btgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00 + MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00 + MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 + >; + }; + + pinctrl_usbotg1pwrgrp: usbotg1pwrgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi new file mode 100644 index 000000000000..995b44efb1b6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -0,0 +1,440 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +#include "imx8mm.dtsi" +#include + +/ { + model = "PHYTEC phyCORE-i.MX8MM"; + compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm"; + + aliases { + rtc0 = &rv3028; + rtc1 = &snvs_rtc; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + reg_vdd_3v3_s: regulator-vdd-3v3-s { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_3V3_S"; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +/* Ethernet */ +&fec1 { + fsl,magic-packet; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + enet-phy-lane-no-swap; + ti,clk-output-sel = ; + ti,fifo-depth = ; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + reg = <0>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + }; + }; +}; + +/* SPI Flash */ +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + som_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&gpio1 { + gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT", + "", "", "", "RESET_ETHPHY", + "", "", "nENABLE_FLATLINK"; +}; + +/* I2C1 */ +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default","gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic@8 { + compatible = "nxp,pf8121a"; + reg = <0x08>; + + regulators { + reg_nvcc_sd1: ldo1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "NVCC_SD1 (LDO1)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_nvcc_sd2: ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "NVCC_SD2 (LDO2)"; + vselect-en; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vcc_enet: ldo3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2500000>; + regulator-min-microvolt = <1500000>; + regulator-name = "VCC_ENET_2V5 (LDO3)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdda_1v8: ldo4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1500000>; + regulator-name = "VDDA_1V8 (LDO4)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt = <1500000>; + regulator-suspend-max-microvolt = <1500000>; + }; + }; + + reg_soc_vdda_phy: buck1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <400000>; + regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt = <400000>; + regulator-suspend-max-microvolt = <400000>; + }; + }; + + reg_vdd_gpu_dram: buck2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <1000000>; + regulator-name = "VDD_GPU_DRAM (BUCK2)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1000000>; + regulator-suspend-min-microvolt = <1000000>; + }; + }; + + reg_vdd_gpu: buck3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <400000>; + regulator-name = "VDD_VPU (BUCK3)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdd_mipi: buck4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <900000>; + regulator-name = "VDD_MIPI_0P9 (BUCK4)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdd_arm: buck5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <400000>; + regulator-name = "VDD_ARM (BUCK5)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdd_1v8: buck6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDD_1V8 (BUCK6)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1800000>; + regulator-suspend-min-microvolt = <1800000>; + }; + }; + + reg_nvcc_dram: buck7 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "NVCC_DRAM_1P1V (BUCK7)"; + }; + + reg_vsnvs: vsnvs { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "NVCC_SNVS_1P8 (VSNVS)"; + }; + }; + }; + + sn65dsi83: bridge@2d { + compatible = "ti,sn65dsi83"; + enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sn65dsi83>; + reg = <0x2d>; + status = "disabled"; + }; + + eeprom@51 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x51>; + vcc-supply = <®_vdd_3v3_s>; + }; + + rv3028: rtc@52 { + compatible = "microcrystal,rv3028"; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + reg = <0x52>; + }; +}; + +/* EMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + keep-power-in-suspend; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + non-removable; + status = "okay"; +}; + +/* Watchdog */ +&wdog1 { + fsl,ext-reset-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0 + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + + pinctrl_sn65dsi83: sn65dsi83grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26 + >; + }; +}; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DE01CCA47C for ; Thu, 23 Jun 2022 14:41:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231571AbiFWOle (ORCPT ); Thu, 23 Jun 2022 10:41:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231731AbiFWOlb (ORCPT ); Thu, 23 Jun 2022 10:41:31 -0400 Received: from mickerik.phytec.de (mickerik.phytec.de [195.145.39.210]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B3A545AFD for ; Thu, 23 Jun 2022 07:41:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1655995285; x=1658587285; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=1Ny/IhS26LkyjgL1J8uUWi3R9TUW1Za6jMAEjBfF5qw=; b=tZJ0/z16Czm9x8hAfZSkxaW4BNMkCCexx8LTSUVuPrtsMVOfz9nl3M5uovdLdHnf m69BO2C/U4n55qKowfbJ4N+ANqaGz88H4VQ71h8MTUI3/wKPIEEHF1XFa8+/FkWk CKYSw7bdqr3I3X80q88ssl2wl1bB3Bx4a9LYSvBgAZw=; X-AuditID: c39127d2-b3a2d70000001dbe-bd-62b47b95290a Received: from idefix.phytec.de (Unknown_Domain [172.25.0.20]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 23.50.07614.59B74B26; Thu, 23 Jun 2022 16:41:25 +0200 (CEST) Received: from augenblix2.phytec.de ([172.25.0.51]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2022062316412515-228336 ; Thu, 23 Jun 2022 16:41:25 +0200 From: Teresa Remmet To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Fabio Estevam , NXP Linux Team , Sascha Hauer , upstream@phytec.de Subject: [PATCH v4 3/3] arm64: dts: freescale: Add phyBOARD-Polis-i.MX8MM support Date: Thu, 23 Jun 2022 16:41:24 +0200 Message-Id: <20220623144124.1821570-3-t.remmet@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220623144124.1821570-1-t.remmet@phytec.de> References: <20220623144124.1821570-1-t.remmet@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 23.06.2022 16:41:25, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 23.06.2022 16:41:25 X-TNEFEvaluated: 1 Content-Transfer-Encoding: quoted-printable X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrHLMWRmVeSWpSXmKPExsWyRpJBRHdq9ZYkg3NHZSzmHznHavHwqr9F 34uHzBabHl9jtej6tZLZonXvEXaLv9s3sVi82CLuwOGxc9Zddo9NqzrZPO5c28PmsXlJvcfG dzuYPPr/Gnh83iQXwB7FZZOSmpNZllqkb5fAlTGraStLwenbjBXt59qYGxgPbmXsYuTkkBAw kVjx4yBzFyMXh5DANkaJq03/GCGc84wSNx5MYAapYhPQkHi64jQTiC0i4CLR+WAdC0gRs0Aj k8SOYxfAioQFAiXuvd/IAmKzCKhKfJ/8FayBV8BS4vK66+wQ6+QlZl76DmZzClhJfN83FcwW AqpZ9foqM0S9oMTJmU/AFkgIXGGUODXhHzNEs5DE6cVnwWxmAW2JZQtfM09gFJiFpGcWktQC RqZVjEK5mcnZqUWZ2XoFGZUlqcl6KambGIFhfnii+qUdjH1zPA4xMnEwHmKU4GBWEuF98X9z khBvSmJlVWpRfnxRaU5q8SFGaQ4WJXHe+z1MiUIC6YklqdmpqQWpRTBZJg5OqQZGzj6+UK/N uvrVG730jG5yvZObWzNXjPcMwyczw+fNcnfbty9pFj9k3vivTY5NYU7htulHp0f4rJM58WjL v2YFw5clJotWHmtQCrK+c2il2fV0qflK/7VfxN/rZmF5Y/yKXaRU7pimREjb6+rMe9nle63O XGi8fUp5Dc+N+xkzemuuXk5cI+CvxFKckWioxVxUnAgAJIGED2ECAAA= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add initial support for phyBOARD-Polis-i.MX8MM. Main features are: * Bluetooth and Wifi * CANFD * eMMC * i2c RTC * Ethernet * PCIe * RS232/RS485 * SD-Card * SPI-NOR flash * USB Signed-off-by: Teresa Remmet --- Changes in v4: - Do not modify reserved iomux bits - Remove eth phy irq due to a recent found hw issue on SoM Changes in v3: - move "enable-active-high" after "gpio" property - Add missing newlines before child nodes - sort i2c devices by address Changes in v2: - added missing space in compatible of imx8mm-phyboard-polis-rdk - removed underscores in node names - fixed indentation of reg=5Fusdhc2=5Fvmmc node - put status always as last property of nodes - updated node name of sn65dsi83 to bridge --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx8mm-phyboard-polis-rdk.dts | 450 ++++++++++++++++++ .../dts/freescale/imx8mm-phycore-som.dtsi | 440 +++++++++++++++++ 3 files changed, 891 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk= .dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 238a83e5b8c6..1e25dec2109b 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -58,6 +58,7 @@ dtb-$(CONFIG=5FARCH=5FMXC) +=3D imx8mm-icore-mx8mm-edimm2= .2.dtb dtb-$(CONFIG=5FARCH=5FMXC) +=3D imx8mm-kontron-n801x-s.dtb dtb-$(CONFIG=5FARCH=5FMXC) +=3D imx8mm-mx8menlo.dtb dtb-$(CONFIG=5FARCH=5FMXC) +=3D imx8mm-nitrogen-r2.dtb +dtb-$(CONFIG=5FARCH=5FMXC) +=3D imx8mm-phyboard-polis-rdk.dtb dtb-$(CONFIG=5FARCH=5FMXC) +=3D imx8mm-tqma8mqml-mba8mx.dtb dtb-$(CONFIG=5FARCH=5FMXC) +=3D imx8mm-var-som-symphony.dtb dtb-$(CONFIG=5FARCH=5FMXC) +=3D imx8mm-venice-gw71xx-0x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/= arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts new file mode 100644 index 000000000000..4a3df2b77b0b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +/dts-v1/; + +#include +#include +#include +#include "imx8mm-phycore-som.dtsi" + +/ { + model =3D "PHYTEC phyBOARD-Polis-i.MX8MM RDK"; + compatible =3D "phytec,imx8mm-phyboard-polis-rdk", + "phytec,imx8mm-phycore-som", "fsl,imx8mm"; + + chosen { + stdout-path =3D &uart3; + }; + + bt=5Fosc=5F32k: bt-lp-clock { + compatible =3D "fixed-clock"; + clock-frequency =3D <32768>; + clock-output-names =3D "bt=5Fosc=5F32k"; + #clock-cells =3D <0>; + }; + + can=5Fosc=5F40m: can-clock { + compatible =3D "fixed-clock"; + clock-frequency =3D <40000000>; + clock-output-names =3D "can=5Fosc=5F40m"; + #clock-cells =3D <0>; + }; + + fan { + compatible =3D "gpio-fan"; + gpios =3D <&gpio4 8 GPIO=5FACTIVE=5FHIGH>; + gpio-fan,speed-map =3D <0 0 + 13000 1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Ffan>; + #cooling-cells =3D <2>; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Fleds>; + + led-0 { + color =3D ; + function =3D LED=5FFUNCTION=5FDISK; + gpios =3D <&gpio1 1 GPIO=5FACTIVE=5FHIGH>; + linux,default-trigger =3D "mmc2"; + }; + + led-1 { + color =3D ; + function =3D LED=5FFUNCTION=5FDISK; + gpios =3D <&gpio1 15 GPIO=5FACTIVE=5FHIGH>; + linux,default-trigger =3D "mmc1"; + }; + + led-2 { + color =3D ; + function =3D LED=5FFUNCTION=5FCPU; + gpios =3D <&gpio1 14 GPIO=5FACTIVE=5FHIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + usdhc1=5Fpwrseq: pwr-seq { + compatible =3D "mmc-pwrseq-simple"; + post-power-on-delay-ms =3D <100>; + power-off-delay-us =3D <60>; + reset-gpios =3D <&gpio2 7 GPIO=5FACTIVE=5FLOW>; + }; + + reg=5Fcan=5Fen: regulator-can-en { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio1 9 GPIO=5FACTIVE=5FLOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Fcan=5Fen>; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "CAN=5FEN"; + startup-delay-us =3D <20>; + }; + + reg=5Fusb=5Fotg1=5Fvbus: regulator-usb-otg1 { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio1 12 GPIO=5FACTIVE=5FHIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Fusbotg1pwrgrp>; + regulator-name =3D "usb=5Fotg1=5Fvbus"; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + }; + + reg=5Fusdhc2=5Fvmmc: regulator-usdhc2 { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio2 19 GPIO=5FACTIVE=5FHIGH>; + enable-active-high; + off-on-delay-us =3D <20000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Freg=5Fusdhc2=5Fvmmc>; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "VSD=5F3V3"; + }; + + reg=5Fvcc=5F3v3: regulator-vcc-3v3 { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "VCC=5F3V3"; + }; +}; + +/* SPI - CAN MCP251XFD */ +&ecspi1 { + cs-gpios =3D <&gpio5 9 GPIO=5FACTIVE=5FLOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Fecspi1>; + status =3D "okay"; + + can0: can@0 { + compatible =3D "microchip,mcp251xfd"; + clocks =3D <&can=5Fosc=5F40m>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <8 IRQ=5FTYPE=5FLEVEL=5FLOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Fcan=5Fint>; + reg =3D <0>; + spi-max-frequency =3D <20000000>; + xceiver-supply =3D <®=5Fcan=5Fen>; + }; +}; + +&gpio1 { + gpio-line-names =3D "nINT=5FETHPHY", "LED=5FRED", "WDOG=5FINT", "X=5FRTC= =5FINT", + "", "", "", "RESET=5FETHPHY", + "CAN=5FnINT", "CAN=5FEN", "nENABLE=5FFLATLINK", "", + "USB=5FOTG=5FVBUS=5FEN", "", "LED=5FGREEN", "LED=5FBLUE"; +}; + +&gpio2 { + gpio-line-names =3D "", "", "", "", + "", "", "BT=5FREG=5FON", "WL=5FREG=5FON", + "BT=5FDEV=5FWAKE", "BT=5FHOST=5FWAKE", "", "", + "X=5FSD2=5FCD=5FB", "", "", "", + "", "", "", "SD2=5FRESET=5FB"; +}; + +&gpio4 { + gpio-line-names =3D "", "", "", "", + "", "", "", "", + "FAN", "miniPCIe=5FnPERST", "", "", + "COEX1", "COEX2"; +}; + +&gpio5 { + gpio-line-names =3D "", "", "", "", + "", "", "", "", + "", "ECSPI1=5FSS0"; +}; + +/* PCIe */ +&pcie0 { + assigned-clocks =3D <&clk IMX8MM=5FCLK=5FPCIE1=5FAUX>, + <&clk IMX8MM=5FCLK=5FPCIE1=5FCTRL>; + assigned-clock-parents =3D <&clk IMX8MM=5FSYS=5FPLL2=5F50M>, + <&clk IMX8MM=5FSYS=5FPLL2=5F250M>; + assigned-clock-rates =3D <10000000>, <250000000>; + clocks =3D <&clk IMX8MM=5FCLK=5FPCIE1=5FROOT>, <&clk IMX8MM=5FCLK=5FPCIE1= =5FAUX>, + <&clk IMX8MM=5FCLK=5FPCIE1=5FPHY>; + clock-names =3D "pcie", "pcie=5Faux", "pcie=5Fbus"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Fpcie>; + reset-gpio =3D <&gpio4 9 GPIO=5FACTIVE=5FLOW>; + status =3D "okay"; +}; + +&pcie=5Fphy { + clocks =3D <&clk IMX8MM=5FCLK=5FPCIE1=5FPHY>; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode =3D ; + fsl,tx-deemph-gen1 =3D <0x2d>; + fsl,tx-deemph-gen2 =3D <0xf>; + status =3D "okay"; +}; + +&rv3028 { + trickle-resistor-ohms =3D <3000>; +}; + +&snvs=5Fpwrkey { + status =3D "okay"; +}; + +/* UART - RS232/RS485 */ +&uart1 { + assigned-clocks =3D <&clk IMX8MM=5FCLK=5FUART1>; + assigned-clock-parents =3D <&clk IMX8MM=5FSYS=5FPLL1=5F80M>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Fuart1>; + uart-has-rtscts; + status =3D "okay"; +}; + +/* UART - Sterling-LWB Bluetooth */ +&uart2 { + assigned-clocks =3D <&clk IMX8MM=5FCLK=5FUART2>; + assigned-clock-parents =3D <&clk IMX8MM=5FSYS=5FPLL1=5F80M>; + fsl,dte-mode; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Fuart2=5Fbt>; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + compatible =3D "brcm,bcm43438-bt"; + clocks =3D <&bt=5Fosc=5F32k>; + clock-names =3D "lpo"; + device-wakeup-gpios =3D <&gpio2 8 GPIO=5FACTIVE=5FHIGH>; + interrupt-names =3D "host-wakeup"; + interrupt-parent =3D <&gpio2>; + interrupts =3D <9 IRQ=5FTYPE=5FEDGE=5FBOTH>; + max-speed =3D <2000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Fbt>; + shutdown-gpios =3D <&gpio2 6 GPIO=5FACTIVE=5FHIGH>; + vddio-supply =3D <®=5Fvcc=5F3v3>; + }; +}; + +/* UART - console */ +&uart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Fuart3>; + status =3D "okay"; +}; + +/* USB */ +&usbotg1 { + adp-disable; + dr=5Fmode =3D "otg"; + over-current-active-low; + samsung,picophy-pre-emp-curr-control =3D <3>; + samsung,picophy-dc-vol-level-adjust =3D <7>; + srp-disable; + vbus-supply =3D <®=5Fusb=5Fotg1=5Fvbus>; + status =3D "okay"; +}; + +&usbotg2 { + disable-over-current; + dr=5Fmode =3D "host"; + samsung,picophy-pre-emp-curr-control =3D <3>; + samsung,picophy-dc-vol-level-adjust =3D <7>; + status =3D "okay"; +}; + +/* SDIO - Sterling-LWB Wifi */ +&usdhc1 { + assigned-clocks =3D <&clk IMX8MM=5FCLK=5FUSDHC1>; + assigned-clock-rates =3D <200000000>; + bus-width =3D <4>; + mmc-pwrseq =3D <&usdhc1=5Fpwrseq>; + non-removable; + no-1-8-v; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Fusdhc1>, <&pinctrl=5Fwlan>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + brcmf: wifi@1 { + compatible =3D "brcm,bcm4329-fmac"; + reg =3D <1>; + }; +}; + +/* SD-Card */ +&usdhc2 { + assigned-clocks =3D <&clk IMX8MM=5FCLK=5FUSDHC2>; + assigned-clock-rates =3D <200000000>; + bus-width =3D <4>; + cd-gpios =3D <&gpio2 12 GPIO=5FACTIVE=5FLOW>; + disable-wp; + pinctrl-names =3D "default", "state=5F100mhz", "state=5F200mhz"; + pinctrl-0 =3D <&pinctrl=5Fusdhc2>, <&pinctrl=5Fusdhc2=5Fgpio>; + pinctrl-1 =3D <&pinctrl=5Fusdhc2=5F100mhz>, <&pinctrl=5Fusdhc2=5Fgpio>; + pinctrl-2 =3D <&pinctrl=5Fusdhc2=5F200mhz>, <&pinctrl=5Fusdhc2=5Fgpio>; + vmmc-supply =3D <®=5Fusdhc2=5Fvmmc>; + vqmmc-supply =3D <®=5Fnvcc=5Fsd2>; + status =3D "okay"; +}; + +&iomuxc { + pinctrl=5Fbt: btgrp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FSD1=5FDATA4=5FGPIO2=5FIO6 0x00 + MX8MM=5FIOMUXC=5FSD1=5FDATA6=5FGPIO2=5FIO8 0x00 + MX8MM=5FIOMUXC=5FSD1=5FDATA7=5FGPIO2=5FIO9 0x00 + >; + }; + + pinctrl=5Fcan=5Fen: can-engrp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FGPIO1=5FIO09=5FGPIO1=5FIO9 0x00 + >; + }; + + pinctrl=5Fcan=5Fint: can-intgrp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FGPIO1=5FIO08=5FGPIO1=5FIO8 0x00 + >; + }; + + pinctrl=5Fecspi1: ecspi1grp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FECSPI1=5FMISO=5FECSPI1=5FMISO 0x80 + MX8MM=5FIOMUXC=5FECSPI1=5FMOSI=5FECSPI1=5FMOSI 0x80 + MX8MM=5FIOMUXC=5FECSPI1=5FSCLK=5FECSPI1=5FSCLK 0x80 + MX8MM=5FIOMUXC=5FECSPI1=5FSS0=5FGPIO5=5FIO9 0x00 + >; + }; + + pinctrl=5Ffan: fan0grp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FSAI1=5FRXD6=5FGPIO4=5FIO8 0x16 + >; + }; + + pinctrl=5Fleds: leds1grp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FGPIO1=5FIO01=5FGPIO1=5FIO1 0x16 + MX8MM=5FIOMUXC=5FGPIO1=5FIO14=5FGPIO1=5FIO14 0x16 + MX8MM=5FIOMUXC=5FGPIO1=5FIO15=5FGPIO1=5FIO15 0x16 + >; + }; + + pinctrl=5Fpcie: pciegrp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FSAI1=5FRXD7=5FGPIO4=5FIO9 0x00 + MX8MM=5FIOMUXC=5FSAI1=5FTXD0=5FGPIO4=5FIO12 0x12 + MX8MM=5FIOMUXC=5FSAI1=5FTXD7=5FGPIO4=5FIO19 0x12 + >; + }; + + pinctrl=5Freg=5Fusdhc2=5Fvmmc: regusdhc2vmmcgrp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FSD2=5FRESET=5FB=5FGPIO2=5FIO19 0x40 + >; + }; + + pinctrl=5Fuart1: uart1grp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FSAI2=5FRXC=5FUART1=5FDCE=5FRX 0x00 + MX8MM=5FIOMUXC=5FSAI2=5FRXD0=5FUART1=5FDCE=5FRTS=5FB 0x00 + MX8MM=5FIOMUXC=5FSAI2=5FRXFS=5FUART1=5FDCE=5FTX 0x00 + MX8MM=5FIOMUXC=5FSAI2=5FTXFS=5FUART1=5FDCE=5FCTS=5FB 0x00 + >; + }; + + pinctrl=5Fuart2=5Fbt: uart2btgrp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FSAI3=5FRXC=5FUART2=5FDTE=5FRTS=5FB 0x00 + MX8MM=5FIOMUXC=5FSAI3=5FRXD=5FUART2=5FDTE=5FCTS=5FB 0x00 + MX8MM=5FIOMUXC=5FSAI3=5FTXC=5FUART2=5FDTE=5FRX 0x00 + MX8MM=5FIOMUXC=5FSAI3=5FTXFS=5FUART2=5FDTE=5FTX 0x00 + >; + }; + + pinctrl=5Fuart3: uart3grp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FUART3=5FRXD=5FUART3=5FDCE=5FRX 0x40 + MX8MM=5FIOMUXC=5FUART3=5FTXD=5FUART3=5FDCE=5FTX 0x40 + >; + }; + + pinctrl=5Fusbotg1pwrgrp: usbotg1pwrgrp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FGPIO1=5FIO12=5FGPIO1=5FIO12 0x00 + >; + }; + + pinctrl=5Fusdhc1: usdhc1grp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FSD1=5FCLK=5FUSDHC1=5FCLK 0x182 + MX8MM=5FIOMUXC=5FSD1=5FCMD=5FUSDHC1=5FCMD 0xc6 + MX8MM=5FIOMUXC=5FSD1=5FDATA0=5FUSDHC1=5FDATA0 0xc6 + MX8MM=5FIOMUXC=5FSD1=5FDATA1=5FUSDHC1=5FDATA1 0xc6 + MX8MM=5FIOMUXC=5FSD1=5FDATA2=5FUSDHC1=5FDATA2 0xc6 + MX8MM=5FIOMUXC=5FSD1=5FDATA3=5FUSDHC1=5FDATA3 0xc6 + >; + }; + + pinctrl=5Fusdhc2=5Fgpio: usdhc2gpiogrp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FSD2=5FCD=5FB=5FGPIO2=5FIO12 0x40 + >; + }; + + pinctrl=5Fusdhc2: usdhc2grp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FGPIO1=5FIO04=5FUSDHC2=5FVSELECT 0x1d0 + MX8MM=5FIOMUXC=5FSD2=5FCLK=5FUSDHC2=5FCLK 0x192 + MX8MM=5FIOMUXC=5FSD2=5FCMD=5FUSDHC2=5FCMD 0x1d2 + MX8MM=5FIOMUXC=5FSD2=5FDATA0=5FUSDHC2=5FDATA0 0x1d2 + MX8MM=5FIOMUXC=5FSD2=5FDATA1=5FUSDHC2=5FDATA1 0x1d2 + MX8MM=5FIOMUXC=5FSD2=5FDATA2=5FUSDHC2=5FDATA2 0x1d2 + MX8MM=5FIOMUXC=5FSD2=5FDATA3=5FUSDHC2=5FDATA3 0x1d2 + >; + }; + + pinctrl=5Fusdhc2=5F100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FGPIO1=5FIO04=5FUSDHC2=5FVSELECT 0x1d0 + MX8MM=5FIOMUXC=5FSD2=5FCLK=5FUSDHC2=5FCLK 0x194 + MX8MM=5FIOMUXC=5FSD2=5FCMD=5FUSDHC2=5FCMD 0x1d4 + MX8MM=5FIOMUXC=5FSD2=5FDATA0=5FUSDHC2=5FDATA0 0x1d4 + MX8MM=5FIOMUXC=5FSD2=5FDATA1=5FUSDHC2=5FDATA1 0x1d4 + MX8MM=5FIOMUXC=5FSD2=5FDATA2=5FUSDHC2=5FDATA2 0x1d4 + MX8MM=5FIOMUXC=5FSD2=5FDATA3=5FUSDHC2=5FDATA3 0x1d4 + >; + }; + + pinctrl=5Fusdhc2=5F200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FGPIO1=5FIO04=5FUSDHC2=5FVSELECT 0x1d0 + MX8MM=5FIOMUXC=5FSD2=5FCLK=5FUSDHC2=5FCLK 0x196 + MX8MM=5FIOMUXC=5FSD2=5FCMD=5FUSDHC2=5FCMD 0x1d6 + MX8MM=5FIOMUXC=5FSD2=5FDATA0=5FUSDHC2=5FDATA0 0x1d6 + MX8MM=5FIOMUXC=5FSD2=5FDATA1=5FUSDHC2=5FDATA1 0x1d6 + MX8MM=5FIOMUXC=5FSD2=5FDATA2=5FUSDHC2=5FDATA2 0x1d6 + MX8MM=5FIOMUXC=5FSD2=5FDATA3=5FUSDHC2=5FDATA3 0x1d6 + >; + }; + + pinctrl=5Fwlan: wlangrp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FSD1=5FDATA5=5FGPIO2=5FIO7 0x00 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/a= rm64/boot/dts/freescale/imx8mm-phycore-som.dtsi new file mode 100644 index 000000000000..995b44efb1b6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -0,0 +1,440 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +#include "imx8mm.dtsi" +#include + +/ { + model =3D "PHYTEC phyCORE-i.MX8MM"; + compatible =3D "phytec,imx8mm-phycore-som", "fsl,imx8mm"; + + aliases { + rtc0 =3D &rv3028; + rtc1 =3D &snvs=5Frtc; + }; + + memory@40000000 { + device=5Ftype =3D "memory"; + reg =3D <0x0 0x40000000 0 0x80000000>; + }; + + reg=5Fvdd=5F3v3=5Fs: regulator-vdd-3v3-s { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "VDD=5F3V3=5FS"; + }; +}; + +&A53=5F0 { + cpu-supply =3D <®=5Fvdd=5Farm>; +}; + +&A53=5F1 { + cpu-supply =3D <®=5Fvdd=5Farm>; +}; + +&A53=5F2 { + cpu-supply =3D <®=5Fvdd=5Farm>; +}; + +&A53=5F3 { + cpu-supply =3D <®=5Fvdd=5Farm>; +}; + +&ddrc { + operating-points-v2 =3D <&ddrc=5Fopp=5Ftable>; + + ddrc=5Fopp=5Ftable: opp-table { + compatible =3D "operating-points-v2"; + + opp-25M { + opp-hz =3D /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz =3D /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz =3D /bits/ 64 <750000000>; + }; + }; +}; + +/* Ethernet */ +&fec1 { + fsl,magic-packet; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Ffec1>; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + enet-phy-lane-no-swap; + ti,clk-output-sel =3D ; + ti,fifo-depth =3D ; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + reg =3D <0>; + reset-gpios =3D <&gpio1 7 GPIO=5FACTIVE=5FHIGH>; + reset-assert-us =3D <1000>; + reset-deassert-us =3D <1000>; + }; + }; +}; + +/* SPI Flash */ +&flexspi { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Fflexspi0>; + status =3D "okay"; + + som=5Fflash: flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <80000000>; + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <1>; + }; +}; + +&gpio1 { + gpio-line-names =3D "nINT=5FETHPHY", "", "WDOG=5FINT", "X=5FRTC=5FINT", + "", "", "", "RESET=5FETHPHY", + "", "", "nENABLE=5FFLATLINK"; +}; + +/* I2C1 */ +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default","gpio"; + pinctrl-0 =3D <&pinctrl=5Fi2c1>; + pinctrl-1 =3D <&pinctrl=5Fi2c1=5Fgpio>; + scl-gpios =3D <&gpio5 14 (GPIO=5FACTIVE=5FHIGH | GPIO=5FOPEN=5FDRAIN)>; + sda-gpios =3D <&gpio5 15 (GPIO=5FACTIVE=5FHIGH | GPIO=5FOPEN=5FDRAIN)>; + status =3D "okay"; + + pmic@8 { + compatible =3D "nxp,pf8121a"; + reg =3D <0x08>; + + regulators { + reg=5Fnvcc=5Fsd1: ldo1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "NVCC=5FSD1 (LDO1)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg=5Fnvcc=5Fsd2: ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "NVCC=5FSD2 (LDO2)"; + vselect-en; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg=5Fvcc=5Fenet: ldo3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <2500000>; + regulator-min-microvolt =3D <1500000>; + regulator-name =3D "VCC=5FENET=5F2V5 (LDO3)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg=5Fvdda=5F1v8: ldo4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1500000>; + regulator-name =3D "VDDA=5F1V8 (LDO4)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt =3D <1500000>; + regulator-suspend-max-microvolt =3D <1500000>; + }; + }; + + reg=5Fsoc=5Fvdda=5Fphy: buck1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <900000>; + regulator-min-microvolt =3D <400000>; + regulator-name =3D "VDD=5FSOC=5FVDDA=5FPHY=5F0P8 (BUCK1)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt =3D <400000>; + regulator-suspend-max-microvolt =3D <400000>; + }; + }; + + reg=5Fvdd=5Fgpu=5Fdram: buck2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1000000>; + regulator-min-microvolt =3D <1000000>; + regulator-name =3D "VDD=5FGPU=5FDRAM (BUCK2)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt =3D <1000000>; + regulator-suspend-min-microvolt =3D <1000000>; + }; + }; + + reg=5Fvdd=5Fgpu: buck3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1000000>; + regulator-min-microvolt =3D <400000>; + regulator-name =3D "VDD=5FVPU (BUCK3)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg=5Fvdd=5Fmipi: buck4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1050000>; + regulator-min-microvolt =3D <900000>; + regulator-name =3D "VDD=5FMIPI=5F0P9 (BUCK4)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg=5Fvdd=5Farm: buck5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1050000>; + regulator-min-microvolt =3D <400000>; + regulator-name =3D "VDD=5FARM (BUCK5)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg=5Fvdd=5F1v8: buck6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "VDD=5F1V8 (BUCK6)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt =3D <1800000>; + regulator-suspend-min-microvolt =3D <1800000>; + }; + }; + + reg=5Fnvcc=5Fdram: buck7 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1100000>; + regulator-min-microvolt =3D <1100000>; + regulator-name =3D "NVCC=5FDRAM=5F1P1V (BUCK7)"; + }; + + reg=5Fvsnvs: vsnvs { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "NVCC=5FSNVS=5F1P8 (VSNVS)"; + }; + }; + }; + + sn65dsi83: bridge@2d { + compatible =3D "ti,sn65dsi83"; + enable-gpios =3D <&gpio1 10 GPIO=5FACTIVE=5FLOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Fsn65dsi83>; + reg =3D <0x2d>; + status =3D "disabled"; + }; + + eeprom@51 { + compatible =3D "atmel,24c32"; + pagesize =3D <32>; + reg =3D <0x51>; + vcc-supply =3D <®=5Fvdd=5F3v3=5Fs>; + }; + + rv3028: rtc@52 { + compatible =3D "microcrystal,rv3028"; + interrupts =3D <3 IRQ=5FTYPE=5FLEVEL=5FLOW>; + interrupt-parent =3D <&gpio1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Frtc>; + reg =3D <0x52>; + }; +}; + +/* EMMC */ +&usdhc3 { + assigned-clocks =3D <&clk IMX8MM=5FCLK=5FUSDHC3=5FROOT>; + assigned-clock-rates =3D <400000000>; + bus-width =3D <8>; + keep-power-in-suspend; + pinctrl-names =3D "default", "state=5F100mhz", "state=5F200mhz"; + pinctrl-0 =3D <&pinctrl=5Fusdhc3>; + pinctrl-1 =3D <&pinctrl=5Fusdhc3=5F100mhz>; + pinctrl-2 =3D <&pinctrl=5Fusdhc3=5F200mhz>; + non-removable; + status =3D "okay"; +}; + +/* Watchdog */ +&wdog1 { + fsl,ext-reset-output; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl=5Fwdog>; + status =3D "okay"; +}; + +&iomuxc { + pinctrl=5Ffec1: fec1grp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FENET=5FMDC=5FENET1=5FMDC 0x2 + MX8MM=5FIOMUXC=5FENET=5FMDIO=5FENET1=5FMDIO 0x2 + MX8MM=5FIOMUXC=5FENET=5FRD0=5FENET1=5FRGMII=5FRD0 0x90 + MX8MM=5FIOMUXC=5FENET=5FRD1=5FENET1=5FRGMII=5FRD1 0x90 + MX8MM=5FIOMUXC=5FENET=5FRD2=5FENET1=5FRGMII=5FRD2 0x90 + MX8MM=5FIOMUXC=5FENET=5FRD3=5FENET1=5FRGMII=5FRD3 0x90 + MX8MM=5FIOMUXC=5FENET=5FRXC=5FENET1=5FRGMII=5FRXC 0x90 + MX8MM=5FIOMUXC=5FENET=5FRX=5FCTL=5FENET1=5FRGMII=5FRX=5FCTL 0x90 + MX8MM=5FIOMUXC=5FENET=5FTD0=5FENET1=5FRGMII=5FTD0 0x16 + MX8MM=5FIOMUXC=5FENET=5FTD1=5FENET1=5FRGMII=5FTD1 0x16 + MX8MM=5FIOMUXC=5FENET=5FTD2=5FENET1=5FRGMII=5FTD2 0x16 + MX8MM=5FIOMUXC=5FENET=5FTD3=5FENET1=5FRGMII=5FTD3 0x16 + MX8MM=5FIOMUXC=5FENET=5FTXC=5FENET1=5FRGMII=5FTXC 0x16 + MX8MM=5FIOMUXC=5FENET=5FTX=5FCTL=5FENET1=5FRGMII=5FTX=5FCTL 0x16 + MX8MM=5FIOMUXC=5FGPIO1=5FIO07=5FGPIO1=5FIO7 0x10 + >; + }; + + pinctrl=5Fflexspi0: flexspi0grp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FNAND=5FALE=5FQSPI=5FA=5FSCLK 0x1c2 + MX8MM=5FIOMUXC=5FNAND=5FCE0=5FB=5FQSPI=5FA=5FSS0=5FB 0x82 + MX8MM=5FIOMUXC=5FNAND=5FDATA00=5FQSPI=5FA=5FDATA0 0x82 + MX8MM=5FIOMUXC=5FNAND=5FDATA01=5FQSPI=5FA=5FDATA1 0x82 + MX8MM=5FIOMUXC=5FNAND=5FDATA02=5FQSPI=5FA=5FDATA2 0x82 + MX8MM=5FIOMUXC=5FNAND=5FDATA03=5FQSPI=5FA=5FDATA3 0x82 + >; + }; + + pinctrl=5Fi2c1: i2c1grp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FI2C1=5FSDA=5FI2C1=5FSDA 0x400001c0 + MX8MM=5FIOMUXC=5FI2C1=5FSCL=5FI2C1=5FSCL 0x400001c0 + >; + }; + + pinctrl=5Fi2c1=5Fgpio: i2c1gpiogrp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FI2C1=5FSDA=5FGPIO5=5FIO15 0x1e0 + MX8MM=5FIOMUXC=5FI2C1=5FSCL=5FGPIO5=5FIO14 0x1e0 + >; + }; + + pinctrl=5Frtc: rtcgrp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FGPIO1=5FIO03=5FGPIO1=5FIO3 0x1c0 + >; + }; + + pinctrl=5Fsn65dsi83: sn65dsi83grp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FGPIO1=5FIO10=5FGPIO1=5FIO10 0x0 + >; + }; + + pinctrl=5Fusdhc3: usdhc3grp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FNAND=5FCLE=5FUSDHC3=5FDATA7 0x1d0 + MX8MM=5FIOMUXC=5FNAND=5FCE1=5FB=5FUSDHC3=5FSTROBE 0x190 + MX8MM=5FIOMUXC=5FNAND=5FCE2=5FB=5FUSDHC3=5FDATA5 0x1d0 + MX8MM=5FIOMUXC=5FNAND=5FCE3=5FB=5FUSDHC3=5FDATA6 0x1d0 + MX8MM=5FIOMUXC=5FNAND=5FDATA04=5FUSDHC3=5FDATA0 0x1d0 + MX8MM=5FIOMUXC=5FNAND=5FDATA05=5FUSDHC3=5FDATA1 0x1d0 + MX8MM=5FIOMUXC=5FNAND=5FDATA06=5FUSDHC3=5FDATA2 0x1d0 + MX8MM=5FIOMUXC=5FNAND=5FDATA07=5FUSDHC3=5FDATA3 0x1d0 + MX8MM=5FIOMUXC=5FNAND=5FRE=5FB=5FUSDHC3=5FDATA4 0x1d0 + MX8MM=5FIOMUXC=5FNAND=5FWE=5FB=5FUSDHC3=5FCLK 0x190 + MX8MM=5FIOMUXC=5FNAND=5FWP=5FB=5FUSDHC3=5FCMD 0x1d0 + >; + }; + + pinctrl=5Fusdhc3=5F100mhz: usdhc3-100mhzgrp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FNAND=5FCLE=5FUSDHC3=5FDATA7 0x1d4 + MX8MM=5FIOMUXC=5FNAND=5FCE1=5FB=5FUSDHC3=5FSTROBE 0x194 + MX8MM=5FIOMUXC=5FNAND=5FCE2=5FB=5FUSDHC3=5FDATA5 0x1d4 + MX8MM=5FIOMUXC=5FNAND=5FCE3=5FB=5FUSDHC3=5FDATA6 0x1d4 + MX8MM=5FIOMUXC=5FNAND=5FDATA04=5FUSDHC3=5FDATA0 0x1d4 + MX8MM=5FIOMUXC=5FNAND=5FDATA05=5FUSDHC3=5FDATA1 0x1d4 + MX8MM=5FIOMUXC=5FNAND=5FDATA06=5FUSDHC3=5FDATA2 0x1d4 + MX8MM=5FIOMUXC=5FNAND=5FDATA07=5FUSDHC3=5FDATA3 0x1d4 + MX8MM=5FIOMUXC=5FNAND=5FRE=5FB=5FUSDHC3=5FDATA4 0x1d4 + MX8MM=5FIOMUXC=5FNAND=5FWE=5FB=5FUSDHC3=5FCLK 0x194 + MX8MM=5FIOMUXC=5FNAND=5FWP=5FB=5FUSDHC3=5FCMD 0x1d4 + >; + }; + + pinctrl=5Fusdhc3=5F200mhz: usdhc3-200mhzgrp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FNAND=5FCLE=5FUSDHC3=5FDATA7 0x1d6 + MX8MM=5FIOMUXC=5FNAND=5FCE1=5FB=5FUSDHC3=5FSTROBE 0x196 + MX8MM=5FIOMUXC=5FNAND=5FCE2=5FB=5FUSDHC3=5FDATA5 0x1d6 + MX8MM=5FIOMUXC=5FNAND=5FCE3=5FB=5FUSDHC3=5FDATA6 0x1d6 + MX8MM=5FIOMUXC=5FNAND=5FDATA04=5FUSDHC3=5FDATA0 0x1d6 + MX8MM=5FIOMUXC=5FNAND=5FDATA05=5FUSDHC3=5FDATA1 0x1d6 + MX8MM=5FIOMUXC=5FNAND=5FDATA06=5FUSDHC3=5FDATA2 0x1d6 + MX8MM=5FIOMUXC=5FNAND=5FDATA07=5FUSDHC3=5FDATA3 0x1d6 + MX8MM=5FIOMUXC=5FNAND=5FRE=5FB=5FUSDHC3=5FDATA4 0x1d6 + MX8MM=5FIOMUXC=5FNAND=5FWE=5FB=5FUSDHC3=5FCLK 0x196 + MX8MM=5FIOMUXC=5FNAND=5FWP=5FB=5FUSDHC3=5FCMD 0x1d6 + >; + }; + + pinctrl=5Fwdog: wdoggrp { + fsl,pins =3D < + MX8MM=5FIOMUXC=5FGPIO1=5FIO02=5FWDOG1=5FWDOG=5FB 0x26 + >; + }; +}; --=20 2.25.1