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([117.96.230.192]) by smtp.gmail.com with ESMTPSA id q62-20020a17090a17c400b001ece6f492easm10284001pja.44.2022.06.27.21.40.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:40:43 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v7 1/4] Revert "target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher" Date: Tue, 28 Jun 2022 10:10:25 +0530 Message-Id: <20220628044028.659704-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628044028.659704-1-apatel@ventanamicro.com> References: <20220628044028.659704-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Jun 2022 04:40:48 -0000 This reverts commit 33cc1c0b69e457f5c526f64297353cba6f7bfdb4 because commit eab4776b2badd4088a4f807c9bb3dc453c53dc23 already implements proper mcountinhibit CSR emulation. Signed-off-by: Anup Patel --- target/riscv/cpu_bits.h | 3 --- target/riscv/csr.c | 2 -- 2 files changed, 5 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8724b45c08..b3f7fa7130 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -159,9 +159,6 @@ #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 -/* Machine Counter Setup */ -#define CSR_MCOUNTINHIBIT 0x320 - /* 32-bit only */ #define CSR_MSTATUSH 0x310 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b5734957cf..d65318dcc6 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3642,8 +3642,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, - [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_zero, write_ignore, - .min_priv_ver = PRIV_VERSION_1_11_0 }, [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, -- 2.34.1