From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DFBCCCA47E for ; Tue, 28 Jun 2022 08:19:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240653AbiF1ITP (ORCPT ); Tue, 28 Jun 2022 04:19:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243889AbiF1IS5 (ORCPT ); Tue, 28 Jun 2022 04:18:57 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB9F72CE3C; Tue, 28 Jun 2022 01:17:23 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8774C6120E; Tue, 28 Jun 2022 08:17:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0FCB0C3411D; Tue, 28 Jun 2022 08:17:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656404242; bh=yGob1Vr8BR4JA5385szP2YP45oWt14YDHpLRa/YTWAo=; h=From:To:Cc:Subject:Date:From; b=MFUMNSyqnFUnmN9rqIYktD7pS6DyDfzyFQ3/DpQ8Vu1R2iGJMAiJwN7eiC24Y7CXv 4HJmXB2WlJQ4kijwghtS7WzQmySeFEfKmEHP4YnGL12CkP+0u9vjmels5gUMkjLnsv fvdYa+42pIq+3w/XiQ8GkcfbY8n5F4O/fHFQRtKNCAuL6FMLJpMkCAAt/8AGq7F39J K4k4xS8uhXlzM19PK8jGdYl/IFsj3oTOfUanjwtB3Tl4M8EazO+J57YAslQCCzNPZb BWjHdQdOeRBeptv07mhvw4KAhlVXBQ2Q/hon3+IB9oirpCBsAeUYruOKed3ksK6gqv gCKPOyspzpAuQ== From: guoren@kernel.org To: palmer@rivosinc.com, arnd@arndb.de, mingo@redhat.com, will@kernel.org, longman@redhat.com, boqun.feng@gmail.com Cc: linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Guo Ren Subject: [PATCH V7 0/5] riscv: Add qspinlock support with combo style Date: Tue, 28 Jun 2022 04:17:02 -0400 Message-Id: <20220628081707.1997728-1-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org From: Guo Ren Enable qspinlock and meet the requirements mentioned in a8ad07e5240c9 ("asm-generic: qspinlock: Indicate the use of mixed-size atomics"). RISC-V LR/SC pairs could provide a strong/weak forward guarantee that depends on micro-architecture. And RISC-V ISA spec has given out several limitations to let hardware support strict forward guarantee (RISC-V User ISA - 8.3 Eventual Success of Store-Conditional Instructions): We restricted the length of LR/SC loops to fit within 64 contiguous instruction bytes in the base ISA to avoid undue restrictions on instruction cache and TLB size and associativity. Similarly, we disallowed other loads and stores within the loops to avoid restrictions on data-cache associativity in simple implementations that track the reservation within a private cache. The restrictions on branches and jumps limit the time that can be spent in the sequence. Floating-point operations and integer multiply/divide were disallowed to simplify the operating system’s emulation of these instructions on implementations lacking appropriate hardware support. Software is not forbidden from using unconstrained LR/SC sequences, but portable software must detect the case that the sequence repeatedly fails, then fall back to an alternate code sequence that does not rely on an unconstrained LR/SC sequence. Implementations are permitted to unconditionally fail any unconstrained LR/SC sequence. eg: Some riscv hardware such as BOOMv3 & XiangShan could provide strict & strong forward guarantee (The cache line would be kept in an exclusive state for Backoff cycles, and only this core's interrupt could break the LR/SC pair). Qemu riscv give a weak forward guarantee by wrong implementation currently [1]. Add combo spinlock (ticket & queued) support Some architecture has a flexible requirement on the type of spinlock. Some LL/SC architectures of ISA don't force micro-arch to give a strong forward guarantee. Thus different kinds of memory model micro-arch would come out in one ISA. The ticket lock is suitable for exclusive monitor designed LL/SC micro-arch with limited cores and "!NUMA". The queue-spinlock could deal with NUMA/large-scale scenarios with a strong forward guarantee designed LL/SC micro-arch. The first version of patch was made in 2019.1 [2]. [1] https://github.com/qemu/qemu/blob/master/target/riscv/insn_trans/trans_rva.c.inc [2] https://lore.kernel.org/linux-riscv/20190211043829.30096-1-michaeljclark@mac.com/#r Change V7: - Add combo spinlock (ticket & queued) support - Rename ticket_spinlock.h - Remove unnecessary atomic_read in ticket_spin_value_unlocked Change V6: - Fixup Clang compile problem Reported-by: kernel test robot - Cleanup asm-generic/spinlock.h - Remove changelog in patch main comment part, suggested by Conor.Dooley@microchip.com - Remove "default y if NUMA" in Kconfig Change V5: - Update comment with RISC-V forward guarantee feature. - Back to V3 direction and optimize asm code. Change V4: - Remove custom sub-word xchg implementation - Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 in locking/qspinlock Change V3: - Coding convention by Peter Zijlstra's advices Change V2: - Coding convention in cmpxchg.h - Re-implement short xchg - Remove char & cmpxchg implementations Guo Ren (2): asm-generic: spinlock: Move qspinlock & ticket-lock into generic spinlock.h riscv: Add qspinlock support Guo Ren (5): asm-generic: ticket-lock: Remove unnecessary atomic_read asm-generic: ticket-lock: Use the same struct definitions with qspinlock asm-generic: ticket-lock: Move into ticket_spinlock.h asm-generic: spinlock: Add combo spinlock (ticket & queued) riscv: Add qspinlock support arch/riscv/Kconfig | 9 +++ arch/riscv/include/asm/Kbuild | 2 + arch/riscv/include/asm/cmpxchg.h | 17 +++++ arch/riscv/kernel/setup.c | 4 ++ include/asm-generic/spinlock.h | 81 +++++++++++++---------- include/asm-generic/spinlock_types.h | 12 +--- include/asm-generic/ticket_spinlock.h | 92 +++++++++++++++++++++++++++ kernel/locking/qspinlock.c | 2 + 8 files changed, 174 insertions(+), 45 deletions(-) create mode 100644 include/asm-generic/ticket_spinlock.h -- 2.36.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D951C43334 for ; Tue, 28 Jun 2022 08:17:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: 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linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Guo Ren Subject: [PATCH V7 0/5] riscv: Add qspinlock support with combo style Date: Tue, 28 Jun 2022 04:17:02 -0400 Message-Id: <20220628081707.1997728-1-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220628_011724_435076_0576F83B X-CRM114-Status: GOOD ( 14.33 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org RnJvbTogR3VvIFJlbiA8Z3VvcmVuQGxpbnV4LmFsaWJhYmEuY29tPgoKRW5hYmxlIHFzcGlubG9j ayBhbmQgbWVldCB0aGUgcmVxdWlyZW1lbnRzIG1lbnRpb25lZCBpbiBhOGFkMDdlNTI0MGM5Cigi YXNtLWdlbmVyaWM6IHFzcGlubG9jazogSW5kaWNhdGUgdGhlIHVzZSBvZiBtaXhlZC1zaXplIGF0 b21pY3MiKS4KClJJU0MtViBMUi9TQyBwYWlycyBjb3VsZCBwcm92aWRlIGEgc3Ryb25nL3dlYWsg Zm9yd2FyZCBndWFyYW50ZWUgdGhhdApkZXBlbmRzIG9uIG1pY3JvLWFyY2hpdGVjdHVyZS4gQW5k IFJJU0MtViBJU0Egc3BlYyBoYXMgZ2l2ZW4gb3V0CnNldmVyYWwgbGltaXRhdGlvbnMgdG8gbGV0 IGhhcmR3YXJlIHN1cHBvcnQgc3RyaWN0IGZvcndhcmQgZ3VhcmFudGVlCihSSVNDLVYgVXNlciBJ U0EgLSA4LjMgRXZlbnR1YWwgU3VjY2VzcyBvZiBTdG9yZS1Db25kaXRpb25hbApJbnN0cnVjdGlv bnMpOgpXZSByZXN0cmljdGVkIHRoZSBsZW5ndGggb2YgTFIvU0MgbG9vcHMgdG8gZml0IHdpdGhp biA2NCBjb250aWd1b3VzCmluc3RydWN0aW9uIGJ5dGVzIGluIHRoZSBiYXNlIElTQSB0byBhdm9p ZCB1bmR1ZSByZXN0cmljdGlvbnMgb24KaW5zdHJ1Y3Rpb24gY2FjaGUgYW5kIFRMQiBzaXplIGFu ZCBhc3NvY2lhdGl2aXR5LiBTaW1pbGFybHksIHdlCmRpc2FsbG93ZWQgb3RoZXIgbG9hZHMgYW5k IHN0b3JlcyB3aXRoaW4gdGhlIGxvb3BzIHRvIGF2b2lkIHJlc3RyaWN0aW9ucwpvbiBkYXRhLWNh Y2hlIGFzc29jaWF0aXZpdHkgaW4gc2ltcGxlIGltcGxlbWVudGF0aW9ucyB0aGF0IHRyYWNrIHRo ZQpyZXNlcnZhdGlvbiB3aXRoaW4gYSBwcml2YXRlIGNhY2hlLiBUaGUgcmVzdHJpY3Rpb25zIG9u IGJyYW5jaGVzIGFuZApqdW1wcyBsaW1pdCB0aGUgdGltZSB0aGF0IGNhbiBiZSBzcGVudCBpbiB0 aGUgc2VxdWVuY2UuIEZsb2F0aW5nLXBvaW50Cm9wZXJhdGlvbnMgYW5kIGludGVnZXIgbXVsdGlw bHkvZGl2aWRlIHdlcmUgZGlzYWxsb3dlZCB0byBzaW1wbGlmeSB0aGUKb3BlcmF0aW5nIHN5c3Rl beKAmXMgZW11bGF0aW9uIG9mIHRoZXNlIGluc3RydWN0aW9ucyBvbiBpbXBsZW1lbnRhdGlvbnMK bGFja2luZyBhcHByb3ByaWF0ZSBoYXJkd2FyZSBzdXBwb3J0LgpTb2Z0d2FyZSBpcyBub3QgZm9y YmlkZGVuIGZyb20gdXNpbmcgdW5jb25zdHJhaW5lZCBMUi9TQyBzZXF1ZW5jZXMsIGJ1dApwb3J0 YWJsZSBzb2Z0d2FyZSBtdXN0IGRldGVjdCB0aGUgY2FzZSB0aGF0IHRoZSBzZXF1ZW5jZSByZXBl YXRlZGx5CmZhaWxzLCB0aGVuIGZhbGwgYmFjayB0byBhbiBhbHRlcm5hdGUgY29kZSBzZXF1ZW5j ZSB0aGF0IGRvZXMgbm90IHJlbHkKb24gYW4gdW5jb25zdHJhaW5lZCBMUi9TQyBzZXF1ZW5jZS4g SW1wbGVtZW50YXRpb25zIGFyZSBwZXJtaXR0ZWQgdG8KdW5jb25kaXRpb25hbGx5IGZhaWwgYW55 IHVuY29uc3RyYWluZWQgTFIvU0Mgc2VxdWVuY2UuCgplZzoKU29tZSByaXNjdiBoYXJkd2FyZSBz dWNoIGFzIEJPT012MyAmIFhpYW5nU2hhbiBjb3VsZCBwcm92aWRlIHN0cmljdCAmCnN0cm9uZyBm b3J3YXJkIGd1YXJhbnRlZSAoVGhlIGNhY2hlIGxpbmUgd291bGQgYmUga2VwdCBpbiBhbiBleGNs dXNpdmUKc3RhdGUgZm9yIEJhY2tvZmYgY3ljbGVzLCBhbmQgb25seSB0aGlzIGNvcmUncyBpbnRl cnJ1cHQgY291bGQgYnJlYWsKdGhlIExSL1NDIHBhaXIpLgpRZW11IHJpc2N2IGdpdmUgYSB3ZWFr IGZvcndhcmQgZ3VhcmFudGVlIGJ5IHdyb25nIGltcGxlbWVudGF0aW9uCmN1cnJlbnRseSBbMV0u CgpBZGQgY29tYm8gc3BpbmxvY2sgKHRpY2tldCAmIHF1ZXVlZCkgc3VwcG9ydApTb21lIGFyY2hp dGVjdHVyZSBoYXMgYSBmbGV4aWJsZSByZXF1aXJlbWVudCBvbiB0aGUgdHlwZSBvZiBzcGlubG9j ay4KU29tZSBMTC9TQyBhcmNoaXRlY3R1cmVzIG9mIElTQSBkb24ndCBmb3JjZSBtaWNyby1hcmNo IHRvIGdpdmUgYSBzdHJvbmcKZm9yd2FyZCBndWFyYW50ZWUuIFRodXMgZGlmZmVyZW50IGtpbmRz IG9mIG1lbW9yeSBtb2RlbCBtaWNyby1hcmNoIHdvdWxkCmNvbWUgb3V0IGluIG9uZSBJU0EuIFRo ZSB0aWNrZXQgbG9jayBpcyBzdWl0YWJsZSBmb3IgZXhjbHVzaXZlIG1vbml0b3IKZGVzaWduZWQg TEwvU0MgbWljcm8tYXJjaCB3aXRoIGxpbWl0ZWQgY29yZXMgYW5kICIhTlVNQSIuIFRoZQpxdWV1 ZS1zcGlubG9jayBjb3VsZCBkZWFsIHdpdGggTlVNQS9sYXJnZS1zY2FsZSBzY2VuYXJpb3Mgd2l0 aCBhIHN0cm9uZwpmb3J3YXJkIGd1YXJhbnRlZSBkZXNpZ25lZCBMTC9TQyBtaWNyby1hcmNoLgoK VGhlIGZpcnN0IHZlcnNpb24gb2YgcGF0Y2ggd2FzIG1hZGUgaW4gMjAxOS4xIFsyXS4KClsxXSBo dHRwczovL2dpdGh1Yi5jb20vcWVtdS9xZW11L2Jsb2IvbWFzdGVyL3RhcmdldC9yaXNjdi9pbnNu X3RyYW5zL3RyYW5zX3J2YS5jLmluYwpbMl0gaHR0cHM6Ly9sb3JlLmtlcm5lbC5vcmcvbGludXgt cmlzY3YvMjAxOTAyMTEwNDM4MjkuMzAwOTYtMS1taWNoYWVsamNsYXJrQG1hYy5jb20vI3IKCkNo YW5nZSBWNzoKIC0gQWRkIGNvbWJvIHNwaW5sb2NrICh0aWNrZXQgJiBxdWV1ZWQpIHN1cHBvcnQK IC0gUmVuYW1lIHRpY2tldF9zcGlubG9jay5oCiAtIFJlbW92ZSB1bm5lY2Vzc2FyeSBhdG9taWNf cmVhZCBpbiB0aWNrZXRfc3Bpbl92YWx1ZV91bmxvY2tlZCAgCgpDaGFuZ2UgVjY6CiAtIEZpeHVw IENsYW5nIGNvbXBpbGUgcHJvYmxlbSBSZXBvcnRlZC1ieToga2VybmVsIHRlc3Qgcm9ib3QKICAg PGxrcEBpbnRlbC5jb20+CiAtIENsZWFudXAgYXNtLWdlbmVyaWMvc3BpbmxvY2suaAogLSBSZW1v dmUgY2hhbmdlbG9nIGluIHBhdGNoIG1haW4gY29tbWVudCBwYXJ0LCBzdWdnZXN0ZWQgYnkKICAg Q29ub3IuRG9vbGV5QG1pY3JvY2hpcC5jb20KIC0gUmVtb3ZlICJkZWZhdWx0IHkgaWYgTlVNQSIg aW4gS2NvbmZpZwoKQ2hhbmdlIFY1OgogLSBVcGRhdGUgY29tbWVudCB3aXRoIFJJU0MtViBmb3J3 YXJkIGd1YXJhbnRlZSBmZWF0dXJlLgogLSBCYWNrIHRvIFYzIGRpcmVjdGlvbiBhbmQgb3B0aW1p emUgYXNtIGNvZGUuCgpDaGFuZ2UgVjQ6CiAtIFJlbW92ZSBjdXN0b20gc3ViLXdvcmQgeGNoZyBp bXBsZW1lbnRhdGlvbgogLSBBZGQgQVJDSF9VU0VfUVVFVUVEX1NQSU5MT0NLU19YQ0hHMzIgaW4g bG9ja2luZy9xc3BpbmxvY2sKCkNoYW5nZSBWMzoKIC0gQ29kaW5nIGNvbnZlbnRpb24gYnkgUGV0 ZXIgWmlqbHN0cmEncyBhZHZpY2VzCgpDaGFuZ2UgVjI6CiAtIENvZGluZyBjb252ZW50aW9uIGlu IGNtcHhjaGcuaAogLSBSZS1pbXBsZW1lbnQgc2hvcnQgeGNoZwogLSBSZW1vdmUgY2hhciAmIGNt cHhjaGcgaW1wbGVtZW50YXRpb25zCgpHdW8gUmVuICgyKToKICBhc20tZ2VuZXJpYzogc3Bpbmxv Y2s6IE1vdmUgcXNwaW5sb2NrICYgdGlja2V0LWxvY2sgaW50byBnZW5lcmljCiAgICBzcGlubG9j ay5oCiAgcmlzY3Y6IEFkZCBxc3BpbmxvY2sgc3VwcG9ydAoKR3VvIFJlbiAoNSk6CiAgYXNtLWdl bmVyaWM6IHRpY2tldC1sb2NrOiBSZW1vdmUgdW5uZWNlc3NhcnkgYXRvbWljX3JlYWQKICBhc20t Z2VuZXJpYzogdGlja2V0LWxvY2s6IFVzZSB0aGUgc2FtZSBzdHJ1Y3QgZGVmaW5pdGlvbnMgd2l0 aCBxc3BpbmxvY2sKICBhc20tZ2VuZXJpYzogdGlja2V0LWxvY2s6IE1vdmUgaW50byB0aWNrZXRf c3BpbmxvY2suaAogIGFzbS1nZW5lcmljOiBzcGlubG9jazogQWRkIGNvbWJvIHNwaW5sb2NrICh0 aWNrZXQgJiBxdWV1ZWQpCiAgcmlzY3Y6IEFkZCBxc3BpbmxvY2sgc3VwcG9ydAoKIGFyY2gvcmlz Y3YvS2NvbmZpZyAgICAgICAgICAgICAgICAgICAgfCAgOSArKysKIGFyY2gvcmlzY3YvaW5jbHVk ZS9hc20vS2J1aWxkICAgICAgICAgfCAgMiArCiBhcmNoL3Jpc2N2L2luY2x1ZGUvYXNtL2NtcHhj aGcuaCAgICAgIHwgMTcgKysrKysKIGFyY2gvcmlzY3Yva2VybmVsL3NldHVwLmMgICAgICAgICAg ICAgfCAgNCArKwogaW5jbHVkZS9hc20tZ2VuZXJpYy9zcGlubG9jay5oICAgICAgICB8IDgxICsr KysrKysrKysrKystLS0tLS0tLS0tCiBpbmNsdWRlL2FzbS1nZW5lcmljL3NwaW5sb2NrX3R5cGVz LmggIHwgMTIgKy0tLQogaW5jbHVkZS9hc20tZ2VuZXJpYy90aWNrZXRfc3BpbmxvY2suaCB8IDky ICsrKysrKysrKysrKysrKysrKysrKysrKysrKwoga2VybmVsL2xvY2tpbmcvcXNwaW5sb2NrLmMg ICAgICAgICAgICB8ICAyICsKIDggZmlsZXMgY2hhbmdlZCwgMTc0IGluc2VydGlvbnMoKyksIDQ1 IGRlbGV0aW9ucygtKQogY3JlYXRlIG1vZGUgMTAwNjQ0IGluY2x1ZGUvYXNtLWdlbmVyaWMvdGlj a2V0X3NwaW5sb2NrLmgKCi0tIAoyLjM2LjEKCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fXwpsaW51eC1yaXNjdiBtYWlsaW5nIGxpc3QKbGludXgtcmlzY3ZA bGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xp c3RpbmZvL2xpbnV4LXJpc2N2Cg==