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([117.96.230.192]) by smtp.gmail.com with ESMTPSA id bj28-20020a056a00319c00b0051bc36b7995sm8909621pfb.62.2022.06.28.03.17.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 03:17:52 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v8 0/4] QEMU RISC-V nested virtualization fixes Date: Tue, 28 Jun 2022 15:47:33 +0530 Message-Id: <20220628101737.786681-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=apatel@ventanamicro.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Jun 2022 10:18:03 -0000 This series does fixes and improvements to have nested virtualization on QEMU RISC-V. These patches can also be found in riscv_nested_fixes_v8 branch at: https://github.com/avpatel/qemu.git The RISC-V nested virtualization was tested on QEMU RISC-V using Xvisor RISC-V which has required hypervisor support to run another hypervisor as Guest/VM. Changes since 7: - Improve tinst "Addr. Offset" in PATCH3 Changes since v6: - Droppred original PATCH1 and PATCH2 since these are already merged - Added PATCH1 to revert dummy mcountinhibit CSR - Added PATCH2 to fix minimum priv spec version for mcountinhibit CSR - Fixed checkpatch error in PATCH3 - Fixed compile error in PATCH4 Changes since v5: - Correctly set "Addr. Offset" for misaligned load/store traps in PATCH3 - Use offsetof() instead of pointer in PATCH4 Changes since v4: - Updated commit description in PATCH1, PATCH2, and PATCH4 - Use "const" for local array in PATCH5 Changes since v3: - Updated PATCH3 to set special pseudoinstructions in htinst for guest page faults which result due to VS-stage page table walks - Updated warning message in PATCH4 Changes since v2: - Dropped the patch which are already in Alistair's next branch - Set "Addr. Offset" in the transformed instruction for PATCH3 - Print warning in riscv_cpu_realize() if we are disabling an extension due to privilege spec verions mismatch for PATCH4 Changes since v1: - Set write_gva to env->two_stage_lookup which ensures that for HS-mode to HS-mode trap write_gva is true only for HLV/HSV instructions - Included "[PATCH 0/3] QEMU RISC-V priv spec version fixes" patches in this series for easy review - Re-worked PATCH7 to force disable extensions if required priv spec version is not staisfied - Added new PATCH8 to fix "aia=aplic-imsic" mode of virt machine Anup Patel (4): Revert "target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher" target/riscv: Set minumum priv spec version for mcountinhibit target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() target/riscv: Force disable extensions if priv spec version does not match target/riscv/cpu.c | 150 +++++++++++++++--------- target/riscv/cpu.h | 5 + target/riscv/cpu_bits.h | 3 - target/riscv/cpu_helper.c | 235 +++++++++++++++++++++++++++++++++++++- target/riscv/csr.c | 4 +- target/riscv/instmap.h | 45 ++++++++ 6 files changed, 374 insertions(+), 68 deletions(-) -- 2.34.1