From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76A1DC43334 for ; Tue, 28 Jun 2022 17:43:30 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5EFBA843E2; Tue, 28 Jun 2022 19:43:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="gH4+UsZO"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 16A4A843E2; Tue, 28 Jun 2022 19:43:27 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 50B508407A for ; Tue, 28 Jun 2022 19:43:24 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id DA4DEB81E9D; Tue, 28 Jun 2022 17:43:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4662DC341D2; Tue, 28 Jun 2022 17:43:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656438203; bh=mSTIYOOE8mZx0O6+DjvbEZnBpZXA+a/Bu34ep81qCTw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=gH4+UsZOKXct24xji2n/MLsajgEVSTqyPS2GzKFZ5I1hJZN/iGi+0TkkAcaMpf6Xv G64UcewUYyXZ8Uidbuy0YtATgDFi8S0dpgLFi7ZbR2OAMC9JF/ltUVCzLYkA0HjsbV hmE7Zi8RpVUpaBgrEvhFrF3vuMrXKVzPqz1K8FI+7GkqyetRgOk6iUHHflM6KwNDTn ly9lwc8CDePdBhATJ8RpYX6bjQ5XPttif2VZaf8cqP9TTU6Sqi1BUFhQY3f1j7uCZF C6NgXoWLYbVGdepRv2yYMOb1lryNMDs6+J3UKR7zbTGihy1GoHIoCfXrDigEypBhIn NWkkJ2wORGP+w== Received: by pali.im (Postfix) id 067517AE; Tue, 28 Jun 2022 19:43:19 +0200 (CEST) Date: Tue, 28 Jun 2022 19:43:19 +0200 From: Pali =?utf-8?B?Um9ow6Fy?= To: Tom Rini Cc: "Priyanka Jain (OSS)" , "Peng Fan (OSS)" , Qiang Zhao , Shengzhou Liu , Alexander Graf , Bin Meng , Wolfgang Denk , Sinan Akman , u-boot@lists.denx.de Subject: Re: [PATCH v3] powerpc: mpc85xx: Set TEXT_BASE addresses to real base values Message-ID: <20220628174319.litdr5rwkxtsfwhy@pali> References: <4fea4901-2d25-b867-617b-e03c152cffce@oss.nxp.com> <20220616121944.7841-1-pali@kernel.org> <20220628145223.GK1146598@bill-the-cat> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220628145223.GK1146598@bill-the-cat> User-Agent: NeoMutt/20180716 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Tuesday 28 June 2022 10:52:23 Tom Rini wrote: > On Thu, Jun 16, 2022 at 02:19:44PM +0200, Pali Rohár wrote: > > > Currently CONFIG_SPL_TEXT_BASE and CONFIG_SYS_TEXT_BASE addresses are > > manually increased by 0x1000 due to .bootpg section. This section has size > > of 0x1000 bytes and is manually put by linker script before .text section > > (and therefore before base address) when CONFIG_SYS_MPC85XX_NO_RESETVEC is > > set. Due to this fact lot of other config options are manually increased by > > 0x1000 value to make correct layout. Note that entry point is not on > > CONFIG_SPL_TEXT_BASE (image+0x1000) but it is really on address > > CONFIG_SPL_TEXT_BASE-0x1000 (means at the start of the image). > > > > Cleanup handling of .bootpg section when CONFIG_SYS_MPC85XX_NO_RESETVEC is > > set. Put .bootpg code directly into .text section and move text base > > address to the start of .bootpg code. And finally remove +0x1000 value from > > lot of config options. With this removal custom PHDRS is not used anymore, > > so remove it too. > > > > After this change entry point would be at CONFIG_SPL_TEXT_BASE and not at > > address -0x1000 anymore. > > > > Tested on P2020 board with SPL and proper U-Boot. > > > > Signed-off-by: Pali Rohár > > Applied to u-boot/next, thanks! > > -- > Tom Thanks!