Re: [PATCH net-next v1 5/9] dt-bindings: net: Add Tegra234 MGBE

[Rob Herring <robh@kernel.org>]

On Thu, Jun 23, 2022 at 01:16:11PM +0530, Bhadram Varka wrote:
> Add device-tree binding documentation for the Tegra234 MGBE ethernet
> controller.
> 
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
> ---
>  .../bindings/net/nvidia,tegra234-mgbe.yaml    | 163 ++++++++++++++++++
>  1 file changed, 163 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
> 
> diff --git a/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
> new file mode 100644
> index 000000000000..d6db43e60ab8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
> @@ -0,0 +1,163 @@
> +# SPDX-License-Identifier: GPL-2.0

Dual license. checkpatch.pl will tell you this.

> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Tegra234 MGBE Device Tree Bindings

s/Device Tree Bindings/???bit Ethernet Controller/

> +
> +maintainers:
> +  - Thierry Reding <treding@nvidia.com>
> +  - Jon Hunter <jonathanh@nvidia.com>
> +
> +properties:
> +
> +  compatible:
> +    const: nvidia,tegra234-mgbe
> +
> +  reg:
> +    minItems: 3
> +    maxItems: 3
> +
> +  reg-names:
> +    items:
> +      - const: hypervisor
> +      - const: mac
> +      - const: xpcs

Is this really part of the same block? You don't have a PHY (the one in 
front of the ethernet PHY) and PCS is sometimes part of the PHY.

> +
> +  interrupts:
> +    minItems: 1
> +
> +  interrupt-names:
> +    items:
> +      - const: common

Just drop interrupt-names. Not a useful name really.

> +
> +  clocks:
> +    minItems: 12
> +    maxItems: 12
> +
> +  clock-names:
> +    minItems: 12
> +    maxItems: 12
> +    contains:
> +      enum:
> +        - mgbe
> +        - mac
> +        - mac-divider
> +        - ptp-ref
> +        - rx-input-m
> +        - rx-input
> +        - tx
> +        - eee-pcs
> +        - rx-pcs-input
> +        - rx-pcs-m
> +        - rx-pcs
> +        - tx-pcs
> +
> +  resets:
> +    minItems: 2
> +    maxItems: 2
> +
> +  reset-names:
> +    contains:
> +      enum:
> +        - mac
> +        - pcs
> +
> +  interconnects:
> +    items:
> +      - description: memory read client
> +      - description: memory write client
> +
> +  interconnect-names:
> +    items:
> +      - const: dma-mem # read
> +      - const: write
> +
> +  iommus:
> +    maxItems: 1
> +
> +  power-domains:
> +    items:
> +      - description: MGBE power-domain

What else would it be? Just 'maxItems: 1'.

> +
> +  phy-handle: true
> +
> +  phy-mode: true

All possible modes are supported by this h/w? Not likely.

> +
> +  mdio:
> +    $ref: mdio.yaml#
> +    unevaluatedProperties: false
> +    description:
> +      Creates and registers an MDIO bus.

That's OS behavior...

> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - interrupt-names
> +  - clocks
> +  - clock-names
> +  - resets
> +  - reset-names
> +  - power-domains
> +  - phy-handle
> +  - phy-mode
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/tegra234-clock.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/memory/tegra234-mc.h>
> +    #include <dt-bindings/power/tegra234-powergate.h>
> +    #include <dt-bindings/reset/tegra234-reset.h>
> +
> +    ethernet@6800000 {
> +        compatible = "nvidia,tegra234-mgbe";
> +        reg = <0x06800000 0x10000>,
> +              <0x06810000 0x10000>,
> +              <0x068a0000 0x10000>;
> +        reg-names = "hypervisor", "mac", "xpcs";
> +        interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
> +        interrupt-names = "common";
> +        clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
> +                 <&bpmp TEGRA234_CLK_MGBE0_MAC>,
> +                 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
> +                 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
> +                 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
> +                 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
> +                 <&bpmp TEGRA234_CLK_MGBE0_TX>,
> +                 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
> +                 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
> +                 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
> +                 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
> +                 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
> +        clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
> +                      "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
> +                      "rx-pcs", "tx-pcs";
> +        resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
> +                 <&bpmp TEGRA234_RESET_MGBE0_PCS>;
> +        reset-names = "mac", "pcs";
> +        interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
> +                        <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
> +        interconnect-names = "dma-mem", "write";
> +        iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
> +        power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
> +
> +        phy-handle = <&mgbe0_phy>;
> +        phy-mode = "usxgmii";
> +
> +        mdio {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            mgbe0_phy: phy@0 {
> +                compatible = "ethernet-phy-ieee802.3-c45";
> +                reg = <0x0>;
> +
> +                #phy-cells = <0>;
> +            };
> +        };
> +    };
> -- 
> 2.17.1
> 
>