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Fri, 01 Jul 2022 20:54:44 -0000 Date: Fri, 1 Jul 2022 14:54:44 -0600 From: Rob Herring To: Shengjiu Wang Subject: Re: [PATCH v2 5/6] ASoC: dt-bindings: fsl_spdif: Add two PLL clock source Message-ID: <20220701205444.GA1511232-robh@kernel.org> References: <1656667961-1799-1-git-send-email-shengjiu.wang@nxp.com> <1656667961-1799-6-git-send-email-shengjiu.wang@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1656667961-1799-6-git-send-email-shengjiu.wang@nxp.com> Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Xiubo.Lee@gmail.com, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lgirdwood@gmail.com, robh+dt@kernel.org, tiwai@suse.com, nicoleotsuka@gmail.com, broonie@kernel.org, festevam@gmail.com, krzk+dt@kernel.org, shengjiu.wang@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On Fri, 01 Jul 2022 17:32:40 +0800, Shengjiu Wang wrote: > Add two PLL clock source, they are the parent clocks of root clock > one is for 8kHz series rates, another one is for 11kHz series rates. > They are optional clocks, if there are such clocks, then driver > can switch between them for supporting more accurate rates. > > Signed-off-by: Shengjiu Wang > --- > Documentation/devicetree/bindings/sound/fsl,spdif.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > Acked-by: Rob Herring From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0A3BC433EF for ; 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Fri, 01 Jul 2022 20:54:44 -0000 Date: Fri, 1 Jul 2022 14:54:44 -0600 From: Rob Herring To: Shengjiu Wang Subject: Re: [PATCH v2 5/6] ASoC: dt-bindings: fsl_spdif: Add two PLL clock source Message-ID: <20220701205444.GA1511232-robh@kernel.org> References: <1656667961-1799-1-git-send-email-shengjiu.wang@nxp.com> <1656667961-1799-6-git-send-email-shengjiu.wang@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1656667961-1799-6-git-send-email-shengjiu.wang@nxp.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Xiubo.Lee@gmail.com, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lgirdwood@gmail.com, robh+dt@kernel.org, tiwai@suse.com, nicoleotsuka@gmail.com, broonie@kernel.org, festevam@gmail.com, krzk+dt@kernel.org, perex@perex.cz, shengjiu.wang@gmail.com Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Fri, 01 Jul 2022 17:32:40 +0800, Shengjiu Wang wrote: > Add two PLL clock source, they are the parent clocks of root clock > one is for 8kHz series rates, another one is for 11kHz series rates. > They are optional clocks, if there are such clocks, then driver > can switch between them for supporting more accurate rates. > > Signed-off-by: Shengjiu Wang > --- > Documentation/devicetree/bindings/sound/fsl,spdif.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > Acked-by: Rob Herring From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3A3AC433EF for ; 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Fri, 01 Jul 2022 13:54:46 -0700 (PDT) Received: from robh.at.kernel.org ([64.188.179.248]) by smtp.gmail.com with ESMTPSA id f65-20020a0284c7000000b00339ddd8adddsm10257382jai.98.2022.07.01.13.54.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Jul 2022 13:54:46 -0700 (PDT) Received: (nullmailer pid 1511267 invoked by uid 1000); Fri, 01 Jul 2022 20:54:44 -0000 Date: Fri, 1 Jul 2022 14:54:44 -0600 From: Rob Herring To: Shengjiu Wang Cc: Xiubo.Lee@gmail.com, nicoleotsuka@gmail.com, shengjiu.wang@gmail.com, linux-kernel@vger.kernel.org, lgirdwood@gmail.com, tiwai@suse.com, devicetree@vger.kernel.org, krzk+dt@kernel.org, perex@perex.cz, linuxppc-dev@lists.ozlabs.org, festevam@gmail.com, alsa-devel@alsa-project.org, broonie@kernel.org, robh+dt@kernel.org Subject: Re: [PATCH v2 5/6] ASoC: dt-bindings: fsl_spdif: Add two PLL clock source Message-ID: <20220701205444.GA1511232-robh@kernel.org> References: <1656667961-1799-1-git-send-email-shengjiu.wang@nxp.com> <1656667961-1799-6-git-send-email-shengjiu.wang@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1656667961-1799-6-git-send-email-shengjiu.wang@nxp.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, 01 Jul 2022 17:32:40 +0800, Shengjiu Wang wrote: > Add two PLL clock source, they are the parent clocks of root clock > one is for 8kHz series rates, another one is for 11kHz series rates. > They are optional clocks, if there are such clocks, then driver > can switch between them for supporting more accurate rates. > > Signed-off-by: Shengjiu Wang > --- > Documentation/devicetree/bindings/sound/fsl,spdif.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > Acked-by: Rob Herring