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From: Jason Gunthorpe <jgg@nvidia.com>
To: Wenpeng Liang <liangwenpeng@huawei.com>
Cc: leon@kernel.org, linux-rdma@vger.kernel.org, linuxarm@huawei.com
Subject: Re: [PATCH for-next 5/5] RDMA/hns: Recover 1bit-ECC error of RAM on chip
Date: Mon, 4 Jul 2022 10:49:35 -0300	[thread overview]
Message-ID: <20220704134935.GA1422797@nvidia.com> (raw)
In-Reply-To: <20220624110845.48184-6-liangwenpeng@huawei.com>

On Fri, Jun 24, 2022 at 07:08:45PM +0800, Wenpeng Liang wrote:
> From: Haoyue Xu <xuhaoyue1@hisilicon.com>
> 
> Since ECC memory maintains a memory system immune to single-bit errors,
> add support for correcting the 1bit-ECC error, which prevents a 1bit-ECC
> error become an uncorrected type error. When a 1bit-ECC error happens in
> the internal ram of the ROCE engine, such as the QPC table, as a 1bit-ECC
> error caused by reading, the ROCE engine only corrects those 1bit ECC
> errors by writing.
> 
> Signed-off-by: Haoyue Xu <xuhaoyue1@hisilicon.com>
> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
> ---
>  drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 195 +++++++++++++++++++++
>  drivers/infiniband/hw/hns/hns_roce_hw_v2.h |  12 ++
>  2 files changed, 207 insertions(+)
> 
> diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
> index 782f09a7f8af..f3be9817a755 100644
> --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
> +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
> @@ -55,6 +55,42 @@ enum {
>  	CMD_RST_PRC_EBUSY,
>  };
>  
> +enum ecc_resource_type {
> +	ECC_RESOURCE_QPC = 0,
> +	ECC_RESOURCE_CQC,
> +	ECC_RESOURCE_MPT,
> +	ECC_RESOURCE_SRQC,
> +	ECC_RESOURCE_GMV,
> +	ECC_RESOURCE_QPC_TIMER,
> +	ECC_RESOURCE_CQC_TIMER,
> +	ECC_RESOURCE_SCCC,
> +	ECC_RESOURCE_COUNT,
> +};
> +
> +static const struct {
> +	char *name;

const char *

> +	ret = hns_roce_cmq_send(hr_dev, &desc, 1);
> +	if (ret) {
> +		dev_err(hr_dev->dev,
> +			"failed to execute cmd to read gmv, ret = %d.\n", ret);
> +		return ret;

Shouldn't all these prints use the IB version of the loggers?

> +static irqreturn_t abnormal_interrupt_others(struct hns_roce_dev *hr_dev)
> +{
> +	struct hns_roce_work *ecc_work;
> +
> +	ecc_work = kzalloc(sizeof(*ecc_work), GFP_ATOMIC);
> +	if (!ecc_work)
> +		return IRQ_NONE;
> +
> +	ecc_work->hr_dev = hr_dev;

Since there is nothing in this work you should just embed it in the
struct hns_roce_dev and use container_of to get the hr_dev. Then there
is no allocation here.

Jason

  reply	other threads:[~2022-07-04 13:49 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-24 11:08 [PATCH for-next 0/5] Supports recovery of on-chip RAM 1bit ECC errors Wenpeng Liang
2022-06-24 11:08 ` [PATCH for-next 1/5] RDMA/hns: Remove unused abnormal interrupt of type RAS Wenpeng Liang
2022-06-24 11:08 ` [PATCH for-next 2/5] RDMA/hns: Fix the wrong type of return value of the interrupt handler Wenpeng Liang
2022-06-24 11:08 ` [PATCH for-next 3/5] RDMA/hns: Fix incorrect clearing of interrupt status register Wenpeng Liang
2022-06-24 11:08 ` [PATCH for-next 4/5] RDMA/hns: Refactor the abnormal interrupt handler function Wenpeng Liang
2022-06-24 11:08 ` [PATCH for-next 5/5] RDMA/hns: Recover 1bit-ECC error of RAM on chip Wenpeng Liang
2022-07-04 13:49   ` Jason Gunthorpe [this message]
2022-07-07 13:32     ` Wenpeng Liang

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