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Mon, 4 Jul 2022 15:51:36 -0400 (EDT) From: Peter Delevoryas To: clg@kaod.org Cc: Peter Delevoryas , Peter Maydell , Andrew Jeffery , Joel Stanley , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/2] hw/i2c/aspeed: Allow machines to set I2CBus Date: Mon, 4 Jul 2022 12:51:34 -0700 Message-Id: <20220704195135.10348-1-peter@pjd.dev> X-Mailer: git-send-email 2.37.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=66.111.4.229; envelope-from=peter@pjd.dev; helo=new3-smtp.messagingengine.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_FMBLA_NEWDOM=1.498, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: TlZUPgK8j+Rt In a multi-SoC board, we want to allow machines to construct shared I2CBus's, so that we can have two SoC I2C controllers attached to a single I2CBus. We already expose read-only access, this just adds a method for setting and using an external I2CBus in the Aspeed I2C bus controller. One issue is that in order to use these methods, the machine needs to reach into the SoC and call these methods on the I2C controller, and we would prefer to keep the abstraction at the SoC level. If we create a set of "aspeed_soc_i2c_get_bus/set_bus" methods though, they will just be one-liners that don't do anything interesting. I would prefer to avoid that if possible, because that doesn't seem scalable if we need to do the same thing for all of the peripherals later. In addition, we are already reaching into the Aspeed SoC to access the flash controller to determine the boot rom size, so there is a precedent that we need to reach into SoC peripherals for data sometimes. Signed-off-by: Peter Delevoryas --- hw/i2c/aspeed_i2c.c | 16 +++++++++++++++- include/hw/i2c/aspeed_i2c.h | 1 + 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 42c6d69b82..00bf58c7a3 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -1236,7 +1236,12 @@ static void aspeed_i2c_bus_realize(DeviceState *dev, Error **errp) sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - s->bus = i2c_init_bus(dev, name); + /* + * If a bus hasn't been provided to the controller, create one from scratch. + */ + if (!s->bus) { + s->bus = i2c_init_bus(dev, name); + } s->slave = i2c_slave_create_simple(s->bus, TYPE_ASPEED_I2C_BUS_SLAVE, 0xff); @@ -1420,3 +1425,12 @@ I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr) return bus; } + +void aspeed_i2c_set_bus(AspeedI2CState *s, int busnr, I2CBus *bus) +{ + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); + + if (busnr >= 0 && busnr < aic->num_busses) { + s->busses[busnr].bus = bus; + } +} diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index 300a89b343..c60f8b291d 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -376,5 +376,6 @@ static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus) } I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr); +void aspeed_i2c_set_bus(AspeedI2CState *s, int busnr, I2CBus *bus); #endif /* ASPEED_I2C_H */ -- 2.37.0