All of lore.kernel.org
 help / color / mirror / Atom feed
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Johan Hovold <johan+linaro@kernel.org>
Cc: "Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Stanimir Varbanov" <svarbanov@mm-sol.com>,
	"Andy Gross" <agross@kernel.org>,
	"Bjorn Andersson" <bjorn.andersson@linaro.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Dmitry Baryshkov" <dmitry.baryshkov@linaro.org>,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 04/10] dt-bindings: PCI: qcom: Add SC8280XP to binding
Date: Sat, 9 Jul 2022 13:30:53 +0530	[thread overview]
Message-ID: <20220709080053.GK5063@thinkpad> (raw)
In-Reply-To: <20220629141000.18111-5-johan+linaro@kernel.org>

On Wed, Jun 29, 2022 at 04:09:54PM +0200, Johan Hovold wrote:
> Add the SC8280XP platform to the binding.
> 
> SC8280XP use four host interrupts for MSI routing so remove the obsolete
> comment referring to newer chipsets supporting one or eight interrupts
> (e.g. for backwards compatibility).
> 
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>

Wondering why 4 on this SoC. Is this what added in downstream or you also
verified it with IP documentation.

Thanks,
Mani

> ---
>  .../devicetree/bindings/pci/qcom,pcie.yaml    | 50 ++++++++++++++++++-
>  1 file changed, 49 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index 8560c65e6f0b..a039f6110322 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -27,6 +27,7 @@ properties:
>        - qcom,pcie-qcs404
>        - qcom,pcie-sc7280
>        - qcom,pcie-sc8180x
> +      - qcom,pcie-sc8280xp
>        - qcom,pcie-sdm845
>        - qcom,pcie-sm8150
>        - qcom,pcie-sm8250
> @@ -181,6 +182,7 @@ allOf:
>              enum:
>                - qcom,pcie-sc7280
>                - qcom,pcie-sc8180x
> +              - qcom,pcie-sc8280xp
>                - qcom,pcie-sm8250
>                - qcom,pcie-sm8450-pcie0
>                - qcom,pcie-sm8450-pcie1
> @@ -596,6 +598,35 @@ allOf:
>            items:
>              - const: pci # PCIe core reset
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,pcie-sc8280xp
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 8
> +          maxItems: 9
> +        clock-names:
> +          minItems: 8
> +          items:
> +            - const: aux # Auxiliary clock
> +            - const: cfg # Configuration clock
> +            - const: bus_master # Master AXI clock
> +            - const: bus_slave # Slave AXI clock
> +            - const: slave_q2a # Slave Q2A clock
> +            - const: ddrss_sf_tbu # PCIe SF TBU clock
> +            - const: noc_aggr_4 # NoC aggregate 4 clock
> +            - const: noc_aggr_south_sf # NoC aggregate South SF clock
> +            - const: cnoc_qx # Configuration NoC QX clock
> +        resets:
> +          maxItems: 1
> +        reset-names:
> +          items:
> +            - const: pci # PCIe core reset
> +
>    - if:
>        not:
>          properties:
> @@ -624,7 +655,6 @@ allOf:
>          - resets
>          - reset-names
>  
> -    # On newer chipsets support either 1 or 8 msi interrupts
>    - if:
>        properties:
>          compatible:
> @@ -660,6 +690,24 @@ allOf:
>                  - const: msi6
>                  - const: msi7
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,pcie-sc8280xp
> +    then:
> +      properties:
> +        interrupts:
> +          minItems: 4
> +          maxItems: 4
> +        interrupt-names:
> +          items:
> +            - const: msi0
> +            - const: msi1
> +            - const: msi2
> +            - const: msi3
> +
>    - if:
>        properties:
>          compatible:
> -- 
> 2.35.1
> 

-- 
மணிவண்ணன் சதாசிவம்

  parent reply	other threads:[~2022-07-09  8:01 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-29 14:09 [PATCH 00/10] PCI: qcom: Add support for SC8280XP and SA8540P Johan Hovold
2022-06-29 14:09 ` [PATCH 01/10] dt-bindings: PCI: qcom: Fix reset conditional Johan Hovold
2022-06-29 14:37   ` Dmitry Baryshkov
2022-07-01  8:29   ` Krzysztof Kozlowski
2022-07-09  7:49   ` Manivannan Sadhasivam
2022-07-13 16:18   ` Bjorn Helgaas
2022-06-29 14:09 ` [PATCH 02/10] dt-bindings: PCI: qcom: Fix msi-interrupt conditional Johan Hovold
2022-06-29 14:37   ` Dmitry Baryshkov
2022-07-01  8:29   ` Krzysztof Kozlowski
2022-07-07 13:34   ` Dmitry Baryshkov
2022-07-07 13:41     ` Dmitry Baryshkov
2022-07-07 13:53       ` Johan Hovold
2022-07-09  7:50   ` Manivannan Sadhasivam
2022-06-29 14:09 ` [PATCH 03/10] dt-bindings: PCI: qcom: Enumerate platforms with single msi interrupt Johan Hovold
2022-07-01  8:33   ` Krzysztof Kozlowski
2022-07-01  8:38     ` Johan Hovold
2022-07-01 18:38       ` Rob Herring
2022-07-04 14:21         ` Johan Hovold
2022-07-01  8:35   ` Krzysztof Kozlowski
2022-07-09  7:58   ` Manivannan Sadhasivam
2022-06-29 14:09 ` [PATCH 04/10] dt-bindings: PCI: qcom: Add SC8280XP to binding Johan Hovold
2022-07-01  8:37   ` Krzysztof Kozlowski
2022-07-01  8:41     ` Johan Hovold
2022-07-09  8:00   ` Manivannan Sadhasivam [this message]
2022-07-11  9:36     ` Johan Hovold
2022-06-29 14:09 ` [PATCH 05/10] dt-bindings: PCI: qcom: Add SA8540P " Johan Hovold
2022-07-01  8:38   ` Krzysztof Kozlowski
2022-07-01  8:42     ` Johan Hovold
2022-07-09  8:02   ` Manivannan Sadhasivam
2022-07-11  9:38     ` Johan Hovold
2022-06-29 14:09 ` [PATCH 06/10] PCI: qcom: Add support for SC8280XP Johan Hovold
2022-07-01 18:29   ` Rob Herring
2022-07-04 14:10     ` Johan Hovold
2022-07-09  8:18   ` Manivannan Sadhasivam
2022-06-29 14:09 ` [PATCH 07/10] PCI: qcom: Add support for SA8540P Johan Hovold
2022-07-01 18:29   ` Rob Herring
2022-07-09  8:19   ` Manivannan Sadhasivam
2022-06-29 14:09 ` [PATCH 08/10] PCI: qcom: Make all optional clocks optional Johan Hovold
2022-07-01 18:34   ` Rob Herring
2022-07-09  8:23   ` Manivannan Sadhasivam
2022-06-29 14:09 ` [PATCH 09/10] PCI: qcom: Clean up IP configurations Johan Hovold
2022-07-01 18:35   ` Rob Herring
2022-07-09  8:25   ` Manivannan Sadhasivam
2022-06-29 14:10 ` [PATCH 10/10] PCI: qcom: Sort device-id table Johan Hovold
2022-07-01  8:40   ` Krzysztof Kozlowski
2022-07-01  8:46     ` Johan Hovold

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220709080053.GK5063@thinkpad \
    --to=manivannan.sadhasivam@linaro.org \
    --cc=agross@kernel.org \
    --cc=bhelgaas@google.com \
    --cc=bjorn.andersson@linaro.org \
    --cc=devicetree@vger.kernel.org \
    --cc=dmitry.baryshkov@linaro.org \
    --cc=johan+linaro@kernel.org \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=kw@linux.com \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lpieralisi@kernel.org \
    --cc=robh+dt@kernel.org \
    --cc=svarbanov@mm-sol.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.